| /linux/drivers/net/ethernet/apm/xgene/ |
| H A D | xgene_enet_cle.c | 17 *reg = SET_VAL(SB_IPFRAG, frag) | in xgene_cle_sband_to_hw()
18 SET_VAL(SB_IPPROT, type) | in xgene_cle_sband_to_hw()
19 SET_VAL(SB_IPVER, ver) | in xgene_cle_sband_to_hw()
20 SET_VAL(SB_HDRLEN, len); in xgene_cle_sband_to_hw()
28 *idt_reg = SET_VAL(IDT_DSTQID, dstqid) | in xgene_cle_idt_to_hw()
29 SET_VAL(IDT_FPSEL1, fpsel) | in xgene_cle_idt_to_hw()
30 SET_VAL(IDT_NFPSEL1, nfpsel); in xgene_cle_idt_to_hw()
32 *idt_reg = SET_VAL(IDT_DSTQID, dstqid) | in xgene_cle_idt_to_hw()
33 SET_VAL(IDT_FPSEL, fpsel) | in xgene_cle_idt_to_hw()
34 SET_VAL(IDT_NFPSEL, nfpsel); in xgene_cle_idt_to_hw()
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| H A D | xgene_enet_ring2.c | 18 ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); in xgene_enet_ring_init()
21 ring_cfg[0] |= SET_VAL(X2_CFGCRID, 2); in xgene_enet_ring_init()
24 ring_cfg[2] |= QCOHERENT | SET_VAL(RINGADDRL, addr); in xgene_enet_ring_init()
27 ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize) in xgene_enet_ring_init()
29 | SET_VAL(RINGADDRH, addr); in xgene_enet_ring_init()
30 ring_cfg[4] |= SET_VAL(X2_SELTHRSH, 1); in xgene_enet_ring_init()
42 ring_cfg[4] |= SET_VAL(X2_RINGTYPE, val); in xgene_enet_ring_set_type()
44 ring_cfg[3] |= SET_VAL(RINGMODE, BUFPOOL_MODE); in xgene_enet_ring_set_type()
52 ring_cfg[4] |= SET_VAL(X2_RECOMTIMEOUT, 0x7); in xgene_enet_ring_set_recombbuf()
163 data = SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK) | in xgene_enet_wr_cmd()
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| H A D | xgene_enet_xgmac.c | 237 data = SET_VAL(TSO_MSS1, data >> TSO_MSS1_POS) | in xgene_xgmac_set_mss()
238 SET_VAL(TSO_MSS0, mss); in xgene_xgmac_set_mss()
240 data = SET_VAL(TSO_MSS1, mss) | SET_VAL(TSO_MSS0, data); in xgene_xgmac_set_mss()
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| /linux/drivers/net/wireless/ath/carl9170/ |
| H A D | phy.c | 461 SET_VAL(AR9170_PHY_SETTLING_SWITCH, val, m->switchSettling); in carl9170_init_phy_from_eeprom()
467 SET_VAL(AR9170_PHY_DESIRED_SZ_PGA, val, m->pgaDesiredSize); in carl9170_init_phy_from_eeprom()
468 SET_VAL(AR9170_PHY_DESIRED_SZ_ADC, val, m->adcDesiredSize); in carl9170_init_phy_from_eeprom()
473 SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF, val, m->txEndToXpaOff); in carl9170_init_phy_from_eeprom()
474 SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF, val, m->txEndToXpaOff); in carl9170_init_phy_from_eeprom()
475 SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAB_ON, val, m->txFrameToXpaOn); in carl9170_init_phy_from_eeprom()
476 SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAA_ON, val, m->txFrameToXpaOn); in carl9170_init_phy_from_eeprom()
481 SET_VAL(AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON, val, m->txEndToRxOn); in carl9170_init_phy_from_eeprom()
491 SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[0]); in carl9170_init_phy_from_eeprom()
497 SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[1]); in carl9170_init_phy_from_eeprom()
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| H A D | mac.c | 416 SET_VAL(AR9170_MAC_BCN_DTIM, v, in carl9170_set_beacon_timers()
434 SET_VAL(AR9170_MAC_BCN_DTIM, v, in carl9170_set_beacon_timers()
459 SET_VAL(AR9170_MAC_BCN_PERIOD, v, ar->global_beacon_int); in carl9170_set_beacon_timers()
460 SET_VAL(AR9170_MAC_PRETBTT, pretbtt, ar->global_pretbtt); in carl9170_set_beacon_timers()
461 SET_VAL(AR9170_MAC_PRETBTT2, pretbtt, ar->global_pretbtt); in carl9170_set_beacon_timers()
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| H A D | tx.c | 785 SET_VAL(AR9170_TX_PHY_MCS, phyrate, txrate->idx); in carl9170_tx_physet()
944 SET_VAL(CARL9170_TX_SUPER_RI_TRIES, txc->s.ri[i], in carl9170_tx_apply_rateset()
1001 SET_VAL(CARL9170_TX_SUPER_MISC_QUEUE, txc->s.misc, hw_queue); in carl9170_tx_prepare()
1004 SET_VAL(CARL9170_TX_SUPER_MISC_VIF_ID, txc->s.misc, cvif->id); in carl9170_tx_prepare()
1062 SET_VAL(CARL9170_TX_SUPER_AMPDU_DENSITY, in carl9170_tx_prepare()
1065 SET_VAL(CARL9170_TX_SUPER_AMPDU_FACTOR, in carl9170_tx_prepare()
1283 SET_VAL(CARL9170_TX_SUPER_MISC_QUEUE, q, in carl9170_tx_drop()
1588 SET_VAL(AR9170_MAC_BCN_HT1_PWR_CTRL, *ht1, 7); in carl9170_tx_beacon_physet()
1589 SET_VAL(AR9170_MAC_BCN_HT1_TPC, *ht1, power); in carl9170_tx_beacon_physet()
1590 SET_VAL(AR9170_MAC_BCN_HT1_CHAIN_MASK, *ht1, chains); in carl9170_tx_beacon_physet()
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| H A D | hw.h | 872 #define SET_VAL(reg, value, newvalue) \ macro
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| /linux/include/linux/mdio/ |
| H A D | mdio-xgene.h | 108 #define SET_VAL(field, val) \ macro
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