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Searched refs:SET_BIT (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_port_common.c115 #define SET_BIT(name) __set_bit(ETHTOOL_LINK_MODE_ ## name ## _BIT, \ in mcdi_to_ethtool_linkset() macro
121 SET_BIT(Backplane); in mcdi_to_ethtool_linkset()
123 SET_BIT(1000baseKX_Full); in mcdi_to_ethtool_linkset()
125 SET_BIT(10000baseKX4_Full); in mcdi_to_ethtool_linkset()
127 SET_BIT(40000baseKR4_Full); in mcdi_to_ethtool_linkset()
133 SET_BIT(FIBRE); in mcdi_to_ethtool_linkset()
135 SET_BIT(1000baseT_Full); in mcdi_to_ethtool_linkset()
136 SET_BIT(1000baseX_Full); in mcdi_to_ethtool_linkset()
139 SET_BIT(10000baseCR_Full); in mcdi_to_ethtool_linkset()
140 SET_BIT(10000baseLR_Full); in mcdi_to_ethtool_linkset()
[all …]
/linux/drivers/net/ethernet/sfc/
H A Dmcdi_port_common.c114 #define SET_BIT(name) __set_bit(ETHTOOL_LINK_MODE_ ## name ## _BIT, \ in mcdi_to_ethtool_linkset() macro
120 SET_BIT(Backplane); in mcdi_to_ethtool_linkset()
122 SET_BIT(1000baseKX_Full); in mcdi_to_ethtool_linkset()
124 SET_BIT(10000baseKX4_Full); in mcdi_to_ethtool_linkset()
126 SET_BIT(40000baseKR4_Full); in mcdi_to_ethtool_linkset()
132 SET_BIT(FIBRE); in mcdi_to_ethtool_linkset()
134 SET_BIT(1000baseT_Full); in mcdi_to_ethtool_linkset()
135 SET_BIT(1000baseX_Full); in mcdi_to_ethtool_linkset()
138 SET_BIT(10000baseCR_Full); in mcdi_to_ethtool_linkset()
139 SET_BIT(10000baseLR_Full); in mcdi_to_ethtool_linkset()
[all …]
/linux/drivers/video/fbdev/kyro/
H A DSTG4000VTG.c34 tmp |= SET_BIT(8); in DisableVGA()
43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2); in StopVTG()
53 tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31)); in StartVTG()
157 tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1); in SetupVTG()
H A DSTG4000Ramdac.c104 tmp &= ~SET_BIT(31); in InitialiseRamdac()
152 tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0); in DisableRamdacOutput()
161 tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0); in EnableRamdacOutput()
H A DSTG4000InitDevice.c296 tmp |= SET_BIT(14); in SetCoreClockPLL()
306 tmp |= SET_BIT(14); in SetCoreClockPLL()
314 tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0)); in SetCoreClockPLL()
318 tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0)); in SetCoreClockPLL()
H A DSTG4000OverlayDevice.c181 tmp |= SET_BIT(31); /* Overlay format to Planer */ in CreateOverlaySurface()
293 tmp |= SET_BIT(7); in EnableOverlayPlane()
298 tmp |= SET_BIT(1); /* video stream */ in EnableOverlayPlane()
H A DSTG4000Reg.h31 #define SET_BIT(n) (1<<(n)) macro
/linux/drivers/usb/storage/
H A Drealtek_cr.c120 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
574 SET_BIT(value, 2); in config_autodelink_after_power_on()
579 SET_BIT(value, 7); in config_autodelink_after_power_on()
592 SET_BIT(value, 2); in config_autodelink_after_power_on()
639 SET_BIT(value, 2); in config_autodelink_before_power_down()
655 SET_BIT(value, 0); in config_autodelink_before_power_down()
657 SET_BIT(value, 2); in config_autodelink_before_power_down()
671 SET_BIT(value, 0); in config_autodelink_before_power_down()
672 SET_BIT(value, 7); in config_autodelink_before_power_down()
676 SET_BIT(value, 2); in config_autodelink_before_power_down()
/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_ring2.c19 ring_cfg[3] |= SET_BIT(X2_DEQINTEN); in xgene_enet_ring_init()
31 ring_cfg[5] |= SET_BIT(X2_QBASE_AM) | SET_BIT(X2_MSG_AM); in xgene_enet_ring_init()
/linux/drivers/scsi/sym53c8xx_2/
H A Dsym_nvram.c235 #define SET_BIT 0 macro
248 case SET_BIT: in S24C16_set_bit()
272 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_start()
284 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_stop()
294 S24C16_set_bit(np, write_bit, gpreg, SET_BIT); in S24C16_do_bit()
488 #undef SET_BIT
/linux/include/linux/mdio/
H A Dmdio-xgene.h111 #define SET_BIT(field) \ macro
/linux/drivers/i2c/busses/
H A Di2c-qup.c120 #define SET_BIT 0x1 macro