Searched refs:SDMA_PKT_POLL_REGMEM_DW5_INTERVAL (Results 1 – 7 of 7) sorted by relevance
340 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v6_0_ring_emit_hdp_flush()1181 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v6_0_ring_emit_pipeline_sync()1241 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v6_0_ring_emit_reg_wait()
343 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v7_0_ring_emit_hdp_flush()1201 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v7_0_ring_emit_pipeline_sync()1242 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v7_0_ring_emit_reg_wait()
1206 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v7_1_ring_emit_pipeline_sync()1246 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v7_1_ring_emit_reg_wait()
2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
849 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ in sdma_v4_0_wait_reg_mem()
4547 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro