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Searched refs:SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h607 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L macro
H A Dsdma1_4_2_sh_mask.h607 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK … macro
H A Dsdma1_4_2_2_sh_mask.h611 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1543 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 macro
H A Doss_2_4_sh_mask.h1713 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 macro
H A Doss_3_0_1_sh_mask.h2233 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 macro
H A Doss_3_0_sh_mask.h2537 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_sh_mask.h2845 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h3213 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h3093 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h2926 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h3202 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK … macro