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Searched refs:SDMA1_BASE__INST5_SEG0 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/
H A Dvega20_ip_offset.h747 #define SDMA1_BASE__INST5_SEG0 0 macro
H A Dsienna_cichlid_ip_offset.h944 #define SDMA1_BASE__INST5_SEG0 0 macro
H A Darct_ip_offset.h1000 #define SDMA1_BASE__INST5_SEG0 0 macro
H A Daldebaran_ip_offset.h1283 #define SDMA1_BASE__INST5_SEG0 0 macro