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Searched refs:SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h543 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT … macro
H A Dsdma0_4_0_sh_mask.h544 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 macro
H A Dsdma0_4_2_sh_mask.h544 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT … macro
H A Dsdma0_4_2_2_sh_mask.h550 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h964 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 macro
H A Doss_2_4_sh_mask.h1048 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 macro
H A Doss_3_0_1_sh_mask.h1066 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 macro
H A Doss_3_0_sh_mask.h1572 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h235 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_sh_mask.h231 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h220 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h197 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h252 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h230 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h253 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT … macro