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Searched refs:SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h410 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK … macro
H A Dsdma0_4_0_sh_mask.h411 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L macro
H A Dsdma0_4_2_sh_mask.h411 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK … macro
H A Dsdma0_4_2_2_sh_mask.h417 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h865 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 macro
H A Doss_2_4_sh_mask.h935 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 macro
H A Doss_3_0_1_sh_mask.h949 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 macro
H A Doss_3_0_sh_mask.h1455 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h103 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_sh_mask.h70 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h63 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h105 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h64 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h100 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK … macro