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Searched refs:SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h412 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK … macro
H A Dsdma0_4_0_sh_mask.h413 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L macro
H A Dsdma0_4_2_sh_mask.h413 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK … macro
H A Dsdma0_4_2_2_sh_mask.h419 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h869 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 macro
H A Doss_2_4_sh_mask.h939 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 macro
H A Doss_3_0_1_sh_mask.h953 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 macro
H A Doss_3_0_sh_mask.h1459 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h105 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_sh_mask.h72 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h65 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h70 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h107 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h66 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h102 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK … macro