| /linux/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 28 #define SCLK_TIMER0 85 macro
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| H A D | rk3188-cru-common.h | 40 #define SCLK_TIMER0 84 macro
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| H A D | rk3128-cru.h | 31 #define SCLK_TIMER0 85 macro
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| H A D | rk3228-cru.h | 31 #define SCLK_TIMER0 85 macro
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| H A D | rv1108-cru.h | 28 #define SCLK_TIMER0 78 macro
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| H A D | rk3308-cru.h | 34 #define SCLK_TIMER0 30 macro
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| H A D | rk3328-cru.h | 36 #define SCLK_TIMER0 47 macro
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| H A D | px30-cru.h | 40 #define SCLK_TIMER0 38 macro
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| H A D | rk3288-cru.h | 40 #define SCLK_TIMER0 85 macro
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 226 COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
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| H A D | clk-rk3128.c | 291 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
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| H A D | clk-rk3228.c | 354 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
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| H A D | clk-rv1108.c | 555 GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
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| H A D | clk-rk3188.c | 441 GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
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| H A D | clk-rk3328.c | 478 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
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| H A D | clk-rk3288.c | 397 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
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| H A D | clk-rk3308.c | 413 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
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| H A D | clk-px30.c | 751 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3066a.dtsi | 267 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
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| H A D | rk3128.dtsi | 629 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3308.dtsi | 548 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
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| H A D | px30.dtsi | 758 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
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