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Searched refs:SCLK_PWM (Results 1 – 10 of 10) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dexynos7-clk.h88 #define SCLK_PWM 11 macro
H A Ds5pv210.h191 #define SCLK_PWM 169 macro
H A Drv1108-cru.h71 #define SCLK_PWM 121 macro
H A Drk3328-cru.h49 #define SCLK_PWM 60 macro
/linux/arch/arm/boot/dts/rockchip/
H A Drv1108.dtsi199 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
210 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
221 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
232 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3328.dtsi485 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
496 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
507 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
518 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
/linux/drivers/clk/samsung/
H A Dclk-s5pv210.c592 GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
H A Dclk-exynos7.c675 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
/linux/drivers/clk/rockchip/
H A Dclk-rv1108.c627 COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,
H A Dclk-rk3328.c465 COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,