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Searched refs:SCALER_DISPCTRL (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/vc4/
H A Dvc4_hvs.c38 VC4_REG32(SCALER_DISPCTRL),
569 reg = HVS_READ(SCALER_DISPCTRL); in vc4_hvs_get_fifo_from_output()
1069 dispctrl = HVS_READ(SCALER_DISPCTRL); in vc4_hvs_mask_underrun()
1074 HVS_WRITE(SCALER_DISPCTRL, dispctrl); in vc4_hvs_mask_underrun()
1091 dispctrl = HVS_READ(SCALER_DISPCTRL); in vc4_hvs_unmask_underrun()
1098 HVS_WRITE(SCALER_DISPCTRL, dispctrl); in vc4_hvs_unmask_underrun()
1136 control = HVS_READ(SCALER_DISPCTRL); in vc4_hvs_irq_handler()
1309 dispctrl = HVS_READ(SCALER_DISPCTRL); in vc4_hvs_hw_init()
1311 HVS_WRITE(SCALER_DISPCTRL, dispctrl); in vc4_hvs_hw_init()
1318 reg = HVS_READ(SCALER_DISPCTRL); in vc4_hvs_hw_init()
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H A Dvc4_kms.c257 dispctrl = HVS_READ(SCALER_DISPCTRL) & in vc4_hvs_pv_muxing_commit()
259 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux); in vc4_hvs_pv_muxing_commit()
286 VC4_GET_FIELD(HVS_READ(SCALER_DISPCTRL), in vc5_hvs_pv_muxing_commit()
302 reg = HVS_READ(SCALER_DISPCTRL); in vc5_hvs_pv_muxing_commit()
303 HVS_WRITE(SCALER_DISPCTRL, in vc5_hvs_pv_muxing_commit()
H A Dvc4_regs.h240 #define SCALER_DISPCTRL 0x00000000 macro