Searched refs:R_BE_SER_PL1_CTRL (Results 1 – 2 of 2) sorted by relevance
311 rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN); in rtw89_pci_ser_setting_be()312 rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK, 1); in rtw89_pci_ser_setting_be()577 rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN); in rtw89_pci_resume_be()584 rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN); in rtw89_pci_resume_be()
954 #define R_BE_SER_PL1_CTRL 0x34A8 macro