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Searched refs:R_BCM1480_IMR_MAILBOX_0_SET_CPU (Results 1 – 2 of 2) sorted by relevance

/linux/arch/mips/sibyte/bcm1480/
H A Dsmp.c26 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
27 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
28 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
29 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
/linux/arch/mips/include/asm/sibyte/
H A Dbcm1480_regs.h376 #define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8 macro