Searched refs:RZ_MTU3_TMDR3 (Results 1 – 2 of 2) sorted by relevance
111 tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3); in rz_mtu3_is_counter_invalid()547 tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3); in rz_mtu3_cascade_counts_enable_get()566 rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3, in rz_mtu3_cascade_counts_enable_set()586 tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3); in rz_mtu3_ext_input_phase_clock_select_get()605 rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3, in rz_mtu3_ext_input_phase_clock_select_set()656 tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3); in rz_mtu3_action_read()
91 #define RZ_MTU3_TMDR3 0x191 /* MTU1 Timer Mode Register 3 */ macro