Searched refs:RX_DESC_NUM (Results 1 – 4 of 4) sorted by relevance
64 #define RX_DESC_NUM 64 macro65 #define RX_DESC_NUM_MASK (RX_DESC_NUM - 1)303 dma_addr_t rx_mapping[RX_DESC_NUM];306 unsigned char *rx_buf[RX_DESC_NUM];314 unsigned char *tx_buf[RX_DESC_NUM];
153 #define RX_DESC_NUM 128 macro156 #define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM-1))236 unsigned char *rx_buf[RX_DESC_NUM];237 dma_addr_t rx_phys[RX_DESC_NUM];330 val = RX_DESC_NUM << PPE_CFG_RX_DEPTH_SHIFT; in hip04_config_fifo()739 for (i = 0; i < RX_DESC_NUM; i++) { in hip04_mac_open()776 for (i = 0; i < RX_DESC_NUM; i++) { in hip04_mac_stop()872 for (i = 0; i < RX_DESC_NUM; i++) { in hip04_alloc_ring()886 for (i = 0; i < RX_DESC_NUM; i++) in hip04_free_ring()939 priv->chan = arg.args[1] * RX_DESC_NUM; in hip04_mac_probe()
173 #define RX_DESC_NUM 1024 macro253 struct sk_buff *rx_skb[RX_DESC_NUM];404 hix5hd2_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM); in hix5hd2_hw_init()477 num = CIRC_SPACE(start, end, RX_DESC_NUM); in hix5hd2_rx_refill()499 pos = dma_ring_incr(pos, RX_DESC_NUM); in hix5hd2_rx_refill()521 num = CIRC_CNT(end, start, RX_DESC_NUM); in hix5hd2_rx()556 pos = dma_ring_incr(pos, RX_DESC_NUM); in hix5hd2_rx()800 for (i = 0; i < RX_DESC_NUM; i++) { in hix5hd2_free_dma_desc_rings()999 priv->rx_fq.count = RX_DESC_NUM; in hix5hd2_init_hw_desc_queue()1000 priv->rx_bq.count = RX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
12 channel, recv channel start from channel * number (RX_DESC_NUM)