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Searched refs:RREG32_SOC15_IP (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v7_0.c425 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v7_0_enable()
428 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
480 mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); in sdma_v7_0_gfx_resume()
513 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v7_0_gfx_resume()
562 doorbell = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); in sdma_v7_0_gfx_resume()
563 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); in sdma_v7_0_gfx_resume()
587 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));
594 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
600 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); in sdma_v12_0_free_ucode_buffer()
609 tmp = RREG32_SOC15_IP(G in sdma_v12_0_free_ucode_buffer()
[all...]
H A Dsdma_v6_0.c399 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_enable()
402 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); in sdma_v6_0_enable()
465 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); in sdma_v6_0_gfx_resume()
498 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_gfx_resume()
544 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); in sdma_v6_0_gfx_resume()
545 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); in sdma_v6_0_gfx_resume()
569 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));
576 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
582 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
592 temp = RREG32_SOC15_IP(G in sdma_v6_0_load_microcode()
[all...]
H A Dsdma_v5_2.c419 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_ctx_switch_enable()
422 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_ctx_switch_enable()
552 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_resume()
573 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, in sdma_v5_2_gfx_resume()
602 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); in sdma_v5_2_gfx_resume()
603 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); in sdma_v5_2_gfx_resume()
637 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
643 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); in sdma_v5_2_rlc_resume()
661 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_load_microcode()
H A Dsdma_v5_0.c353 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_0_ring_set_wptr()
355 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_0_ring_set_wptr()
600 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_ctx_switch_enable()
603 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_ctx_switch_enable()
735 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_resume()
756 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, in sdma_v5_0_gfx_resume()
789 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); in sdma_v5_0_gfx_resume()
790 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, in sdma_v5_0_gfx_resume()
847 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_load_microcode()
H A Dsoc15_common.h70 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0) macro
H A Damdgpu_gmc.c910 RREG32_SOC15_IP(GC, reg) : in amdgpu_gmc_set_vm_fault_masks()
911 RREG32_SOC15_IP(MMHUB, reg); in amdgpu_gmc_set_vm_fault_masks()
H A Damdgpu_amdkfd_gfx_v10_3.c338 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ in hqd_dump_v10_3()
H A Dgmc_v9_0.c497 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v9_0_vm_fault_interrupt_state()
525 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v9_0_vm_fault_interrupt_state()
H A Damdgpu_amdkfd_gfx_v10.c352 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ in kgd_hqd_dump()
H A Dgfx_v11_0.c2036 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_rlc_start()
6125 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_eop_interrupt_state()
6133 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_eop_interrupt_state()
6182 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_eop_irq()
6190 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_eop_irq()
6303 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
6317 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
6349 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_emit_mem_sync()
6363 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_emit_mem_sync()
6394 cp_int_cntl = RREG32_SOC15_IP(G in gfx_v11_ip_print()
[all...]
H A Damdgpu_amdkfd_gfx_v9.c969 reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, inst, mmSPI_CSQ_WF_ACTIVE_COUNT_0) + in get_wave_count()
H A Dsoc15.c464 RREG32_SOC15_IP(GC, reg) : RREG32(reg); in soc15_program_register_sequence()
H A Dgfx_v12_0.c1745 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_rlc_smu_handshake_cntl()
4651 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4659 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4702 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_eop_irq()
4710 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_eop_irq()
4823 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_priv_reg_irq()
4837 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_priv_inst_irq()
4869 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_ip_print()
4883 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_ip_print()
4914 cp_int_cntl = RREG32_SOC15_IP(G in gfx_v12_ip_print()
[all...]
H A Dgfx_v10_0.c5278 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_rlc_smu_handshake_cntl()
8983 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
8989 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9036 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_eop_irq()
9042 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_eop_irq()
9150 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_priv_reg_irq()
9164 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_kiq_set_interrupt_state()
9196 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_kiq_set_interrupt_state()
9210 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_kiq_irq()
9241 cp_int_cntl = RREG32_SOC15_IP(G in gfx_v10_0_emit_mem_sync()
[all...]
H A Dgfx_v9_0.c5993 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); in gfx_v9_0_set_cp_ecc_error_state()
5999 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v9_0_set_cp_ecc_error_state()
6054 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_eop_irq()
6090 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_fault()