Searched refs:RREG32_NO_KIQ (Results 1 – 9 of 9) sorted by relevance
325 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()330 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()339 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()347 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()358 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); in xgpu_vi_mailbox_trans_msg()374 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()379 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_vi_mailbox_rcv_msg()395 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()405 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()504 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_vi_set_mailbox_ack_irq()[all …]
38 RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); in hdp_v5_2_flush_hdp()
1284 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) macro
849 RREG32_NO_KIQ(req); in gmc_v9_0_flush_gpu_tlb()
2996 data = RREG32_NO_KIQ(reg); in gfx_v12_1_update_spm_vmid()
734 *data++ = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_device_mm_access()
4012 data = RREG32_NO_KIQ(reg); in gfx_v12_0_update_spm_vmid()
5660 pre_data = RREG32_NO_KIQ(reg); in gfx_v11_0_update_spm_vmid()
5165 data = RREG32_NO_KIQ(reg); in gfx_v9_0_update_spm_vmid_internal()