Searched refs:RK3288_CLKGEN_DIV (Results 1 – 1 of 1) sorted by relevance
19 #define RK3288_CLKGEN_DIV 2 macro49 unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; in rockchip_mmc_get_internal_phase()92 unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; in rockchip_mmc_set_internal_phase()201 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()203 cclkin = ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()209 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()491 host->bus_hz /= RK3288_CLKGEN_DIV; in dw_mci_rockchip_init()499 ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV); in dw_mci_rockchip_init()501 host->minimum_speed = ret / RK3288_CLKGEN_DIV; in dw_mci_rockchip_init()