Searched refs:RIP_REL_REF (Results 1 – 7 of 7) sorted by relevance
84 RIP_REL_REF(__pgtable_l5_enabled) = 1; in check_la57_support()85 RIP_REL_REF(pgdir_shift) = 48; in check_la57_support()86 RIP_REL_REF(ptrs_per_p4d) = 512; in check_la57_support()87 RIP_REL_REF(page_offset_base) = __PAGE_OFFSET_BASE_L5; in check_la57_support()88 RIP_REL_REF(vmalloc_base) = __VMALLOC_BASE_L5; in check_la57_support()89 RIP_REL_REF(vmemmap_base) = __VMEMMAP_BASE_L5; in check_la57_support()146 pmd_t (*early_pgts)[PTRS_PER_PMD] = RIP_REL_REF(early_dynamic_pgts); in __startup_64()167 RIP_REL_REF(phys_base) = load_delta; in __startup_64()178 pgd = &RIP_REL_REF(early_top_pgt)->pgd; in __startup_64()182 p4d = (p4dval_t *)&RIP_REL_REF(level4_kernel_pgt); in __startup_64()[all …]
305 RIP_REL_REF(sev_status) & MSR_AMD64_SEV_ENABLED) in sme_encrypt_kernel()323 kernel_start = (unsigned long)RIP_REL_REF(_text); in sme_encrypt_kernel()324 kernel_end = ALIGN((unsigned long)RIP_REL_REF(_end), PMD_SIZE); in sme_encrypt_kernel()350 execute_start = workarea_start = (unsigned long)RIP_REL_REF(sme_workarea); in sme_encrypt_kernel()531 RIP_REL_REF(sev_status) = msr = __rdmsr(MSR_AMD64_SEV); in sme_enable()564 RIP_REL_REF(sme_me_mask) = me_mask; in sme_enable()
347 ghcb->protocol_version = RIP_REL_REF(ghcb_version); in svsm_perform_ghcb_protocol()478 return &RIP_REL_REF(cpuid_table_copy); in snp_cpuid_get_table()703 if (!(leaf->fn <= RIP_REL_REF(cpuid_std_range_max) || in snp_cpuid()704 (leaf->fn >= 0x40000000 && leaf->fn <= RIP_REL_REF(cpuid_hyp_range_max)) || in snp_cpuid()705 (leaf->fn >= 0x80000000 && leaf->fn <= RIP_REL_REF(cpuid_ext_range_max)))) in snp_cpuid()1216 RIP_REL_REF(cpuid_std_range_max) = fn->eax; in setup_cpuid_table()1218 RIP_REL_REF(cpuid_hyp_range_max) = fn->eax; in setup_cpuid_table()1220 RIP_REL_REF(cpuid_ext_range_max) = fn->eax; in setup_cpuid_table()1291 if (RIP_REL_REF(snp_vmpl)) { in pvalidate_4k_page()1672 if (!rmpadjust((unsigned long)&RIP_REL_REF(boot_ghcb_page), RMP_PG_SIZE_4K, 1)) in svsm_setup_ca()[all …]
625 if (RIP_REL_REF(sev_cfg).use_cas) in svsm_get_caa()628 return RIP_REL_REF(boot_svsm_caa); in svsm_get_caa()638 if (RIP_REL_REF(sev_cfg).use_cas) in svsm_get_caa_pa()641 return RIP_REL_REF(boot_svsm_caa_pa); in svsm_get_caa_pa()687 if (RIP_REL_REF(sev_cfg).ghcbs_initialized) in svsm_perform_call_protocol()689 else if (RIP_REL_REF(boot_ghcb)) in svsm_perform_call_protocol()690 ghcb = RIP_REL_REF(boot_ghcb); in svsm_perform_call_protocol()699 if (RIP_REL_REF(sev_cfg).ghcbs_initialized) in svsm_perform_call_protocol()870 if (!(RIP_REL_REF(sev_status) & MSR_AMD64_SEV_SNP_ENABLED)) in early_snp_set_memory_private()889 if (!(RIP_REL_REF(sev_status) & MSR_AMD64_SEV_SNP_ENABLED)) in early_snp_set_memory_shared()[all …]
124 #define RIP_REL_REF(var) (*(typeof(&(var)))rip_rel_ptr(&(var))) macro126 #define RIP_REL_REF(var) (var) macro
20 RIP_REL_REF(cc_mask) = mask; in cc_set_mask()
64 return RIP_REL_REF(sme_me_mask); in sme_get_me_mask()