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Searched refs:RG_PE1_PLL_DIVEN (Results 1 – 1 of 1) sorted by relevance

/linux/drivers/phy/ralink/
H A Dphy-mt7621-pci.c40 #define RG_PE1_PLL_DIVEN GENMASK(3, 1) macro
189 RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN, in mt7621_set_phy_for_ssc()
194 FIELD_PREP(RG_PE1_PLL_DIVEN, 0x02)); in mt7621_set_phy_for_ssc()