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Searched refs:RG_PE1_H_PLL_REG (Results 1 – 1 of 1) sorted by relevance

/linux/drivers/phy/ralink/
H A Dphy-mt7621-pci.c34 #define RG_PE1_H_PLL_REG 0x490 macro
144 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, in mt7621_set_phy_for_ssc()
149 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, in mt7621_set_phy_for_ssc()
176 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, in mt7621_set_phy_for_ssc()
187 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, in mt7621_set_phy_for_ssc()