Searched refs:RG_HDMITXPLL_POSDIV_DIV3_CTRL (Results 1 – 2 of 2) sorted by relevance
97 #define RG_HDMITXPLL_POSDIV_DIV3_CTRL BIT(21) macro
133 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV_DIV3_CTRL, div3_ctrl_value); in mtk_hdmi_pll_set_hw()