Searched refs:RG_HDMITXPLL_DIV_CTRL (Results 1 – 2 of 2) sorted by relevance
99 #define RG_HDMITXPLL_DIV_CTRL GENMASK(25, 24) macro
154 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_DIV_CTRL, div_ctrl_value); in mtk_hdmi_pll_set_hw()