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Searched refs:RG_CSI1A_L0_EQ_IS (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-csi-0-5-rx-reg.h36 #define RG_CSI1A_L0_EQ_IS GENMASK(5, 4) macro
H A Dphy-mtk-mipi-csi-0-5.c58 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()
65 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_IS, 1); in mtk_phy_csi_dphy_ana_eq_tune()