Searched refs:RFPGA0_TXGAINSTAGE (Results 1 – 15 of 15) sorted by relevance
183 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; in rtl8723_phy_init_bb_rf_reg_def()184 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; in rtl8723_phy_init_bb_rf_reg_def()185 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; in rtl8723_phy_init_bb_rf_reg_def()186 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in rtl8723_phy_init_bb_rf_reg_def()
188 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; in rtl92d_phy_init_bb_rf_register_definition()190 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; in rtl92d_phy_init_bb_rf_register_definition()192 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; in rtl92d_phy_init_bb_rf_register_definition()194 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in rtl92d_phy_init_bb_rf_register_definition()
1062 #define RFPGA0_TXGAINSTAGE 0x80c macro
143 rtl_set_bbreg(hw, RFPGA0_TXGAINSTAGE, (BXBTXAGC | BXCTXAGC | BXDTXAGC), in _rtl92s_set_antennadiff()147 RFPGA0_TXGAINSTAGE, u4reg_val); in _rtl92s_set_antennadiff()
709 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92s_phy_init_register_definition()710 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92s_phy_init_register_definition()711 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92s_phy_init_register_definition()712 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92s_phy_init_register_definition()
895 #define RFPGA0_TXGAINSTAGE 0x80c macro
426 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()427 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()428 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()429 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()
837 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl88e_phy_init_bb_rf_register_definition()838 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl88e_phy_init_bb_rf_register_definition()839 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl88e_phy_init_bb_rf_register_definition()840 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl88e_phy_init_bb_rf_register_definition()
1280 #define RFPGA0_TXGAINSTAGE 0x80c macro
865 rtl_write_dword(rtlpriv, RFPGA0_TXGAINSTAGE, in rtl92du_hw_init()866 rtl_read_dword(rtlpriv, RFPGA0_TXGAINSTAGE) & ~BIT(31)); in rtl92du_hw_init()
1244 #define RFPGA0_TXGAINSTAGE 0x80c macro
1202 #define RFPGA0_TXGAINSTAGE 0x80c macro
1242 #define RFPGA0_TXGAINSTAGE 0x80c macro
1332 #define RFPGA0_TXGAINSTAGE 0x80c macro
1295 #define RFPGA0_TXGAINSTAGE 0x80c macro