Home
last modified time | relevance | path

Searched refs:REG_WR (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_init_ops.h57 REG_WR(bp, addr + i*4, data[i]); in bnx2x_init_str_wr()
265 REG_WR(bp, addr, op->write.val); in bnx2x_init_block()
497 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); in bnx2x_init_pxp_arb()
498 REG_WR(bp, read_arb_addr[i].add, in bnx2x_init_pxp_arb()
500 REG_WR(bp, read_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
508 REG_WR(bp, write_arb_addr[i].l, in bnx2x_init_pxp_arb()
511 REG_WR(bp, write_arb_addr[i].add, in bnx2x_init_pxp_arb()
514 REG_WR(bp, write_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
519 REG_WR(bp, write_arb_addr[i].l, in bnx2x_init_pxp_arb()
523 REG_WR(bp, write_arb_addr[i].add, in bnx2x_init_pxp_arb()
[all …]
H A Dbnx2x_main.c320 REG_WR(bp, addr, U64_LO(mapping)); in __storm_memset_dma_mapping()
321 REG_WR(bp, addr + 4, U64_HI(mapping)); in __storm_memset_dma_mapping()
480 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); in bnx2x_post_dmae()
482 REG_WR(bp, dmae_reg_go_c[idx], 1); in bnx2x_post_dmae()
872 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); in bnx2x_hc_int_disable()
887 REG_WR(bp, addr, val); in bnx2x_hc_int_disable()
902 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_disable()
1423 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); in bnx2x_send_final_clnup()
1433 REG_WR(bp, comp_addr, 0); in bnx2x_send_final_clnup()
1530 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in bnx2x_pf_flr_clnup()
[all …]
H A Dbnx2x_link.c225 REG_WR(bp, reg, val); in bnx2x_bits_en()
234 REG_WR(bp, reg, val); in bnx2x_bits_dis()
262 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
381 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); in bnx2x_get_epio()
403 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); in bnx2x_set_epio()
407 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); in bnx2x_set_epio()
454 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in bnx2x_ets_e2e3a0_disabled()
463 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_e2e3a0_disabled()
465 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in bnx2x_ets_e2e3a0_disabled()
469 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_e2e3a0_disabled()
[all …]
H A Dbnx2x_init.h233 REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos); in bnx2x_map_q_cos()
238 REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map)); in bnx2x_map_q_cos()
243 REG_WR(bp, reg_addr, reg_bit_map | q_bit_map); in bnx2x_map_q_cos()
255 REG_WR(bp, reg_addr, reg_bit_map); in bnx2x_map_q_cos()
688 REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val); in bnx2x_set_mcp_parity()
712 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr, in bnx2x_disable_blocks_parity()
735 REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
736 REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
737 REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
738 REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
[all …]
H A Dbnx2x_sriov.c102 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags); in bnx2x_vf_igu_ack_sb()
107 REG_WR(bp, igu_addr_ctl, ctl); in bnx2x_vf_igu_ack_sb()
680 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0); in bnx2x_vf_enable_internal()
686 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid); in bnx2x_vf_semi_clear_err()
687 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid); in bnx2x_vf_semi_clear_err()
688 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid); in bnx2x_vf_semi_clear_err()
689 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid); in bnx2x_vf_semi_clear_err()
711 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f)); in bnx2x_vf_pglue_clear_err()
722 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in bnx2x_vf_igu_reset()
723 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in bnx2x_vf_igu_reset()
[all …]
H A Dbnx2x_cmn.h650 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); in bnx2x_igu_ack_sb_gen()
670 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); in bnx2x_hc_ack_sb()
942 REG_WR(bp, PRS_REG_VLAN_TYPE_0, ETH_P_8021AD); in bnx2x_func_start()
943 REG_WR(bp, PBF_REG_VLAN_TYPE_0, ETH_P_8021AD); in bnx2x_func_start()
944 REG_WR(bp, NIG_REG_LLH_E1HOV_TYPE_1, ETH_P_8021AD); in bnx2x_func_start()
1224 REG_WR(bp, addr + (i * 4), data[i]); in __storm_memset_struct()
1335 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + in bnx2x_link_sync_notify()
H A Dbnx2x.h181 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) macro
213 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
218 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
225 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
234 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
H A Dbnx2x_cmn.c1494 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_rx_rings()
1497 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_rx_rings()
2580 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1); in bnx2x_load_cnic()
2610 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); in bnx2x_load_cnic()
H A Dbnx2x_dcb.c68 REG_WR(bp, addr + i, *buff); in bnx2x_write_data()
H A Dbnx2x_sp.c829 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : in bnx2x_set_mac_in_nig()
3569 REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]); in bnx2x_mcast_setup_e1h()
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_hw.c165 REG_WR(p_hwfn, in qed_ptt_set_win()
212 REG_WR(p_hwfn, bar_addr, val); in qed_wr()
305 REG_WR(p_hwfn, in qed_fid_pretend()
322 REG_WR(p_hwfn, in qed_port_pretend()
338 REG_WR(p_hwfn, in qed_port_unpretend()
358 REG_WR(p_hwfn, in qed_port_fid_pretend()
H A Dqed_vf.c89 REG_WR(p_hwfn, in qed_send_msg2pf()
93 REG_WR(p_hwfn, in qed_send_msg2pf()
102 REG_WR(p_hwfn, (uintptr_t)&zone_data->trigger, *((u32 *)&trigger)); in qed_send_msg2pf()
H A Dqed_init_ops.c618 REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE, in qed_gtt_init()
H A Dqed_dev.c2472 REG_WR(p_hwfn, addr, 0); in qed_final_cleanup()
2492 REG_WR(p_hwfn, addr, 0); in qed_final_cleanup()
H A Dqed_sriov.c1224 REG_WR(p_hwfn, in qed_iov_send_response()
3721 REG_WR(p_hwfn, in qed_iov_execute_vf_flr_cleanup()
/linux/drivers/scsi/bnx2i/
H A Dbnx2i.h130 #define REG_WR(__hba, offset, val) \ macro