Searched refs:REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW (Results 1 – 1 of 1) sorted by relevance
108 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30 macro166 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,199 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,459 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, in sn65dsi83_atomic_pre_enable()