Home
last modified time | relevance | path

Searched refs:REG_UPDATE (Results 1 – 25 of 32) sorted by relevance

12

/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
H A Ddcn32_mmhubbub.c97 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1); in mmhubbub32_warmup_mcif()
100 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); in mmhubbub32_warmup_mcif()
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub32_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub32_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub32_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub32_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub32_config_mcif_buf()
119 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub32_config_mcif_buf()
122 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); in mmhubbub32_config_mcif_buf()
123 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub32_config_mcif_buf()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.c97 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1); in mmhubbub3_warmup_mcif()
100 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); in mmhubbub3_warmup_mcif()
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub3_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub3_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub3_config_mcif_buf()
119 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
122 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); in mmhubbub3_config_mcif_buf()
123 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
[all …]
H A Ddcn30_vpg.c79 REG_UPDATE(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, 1); in vpg3_update_generic_info_packet()
82 REG_UPDATE(VPG_GENERIC_PACKET_ACCESS_CTRL, in vpg3_update_generic_info_packet()
113 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
117 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
121 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
125 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
129 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
133 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
137 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
141 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
[all …]
H A Ddcn30_afmt.c56 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_hdmi_audio()
71 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); in afmt3_setup_hdmi_audio()
139 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); in afmt3_se_audio_setup()
143 REG_UPDATE(AFMT_MEM_PWR, AFMT_MEM_PWR_FORCE, 0); in afmt3_se_audio_setup()
156 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); in afmt3_audio_mute_control()
165 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_audio_info_immediate_update()
177 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_dp_audio()
186 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_setup_dp_audio()
189 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); in afmt3_setup_dp_audio()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c83 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1); in dwb2_config_dwb_cnv()
84 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x); in dwb2_config_dwb_cnv()
85 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y); in dwb2_config_dwb_cnv()
86 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb2_config_dwb_cnv()
87 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb2_config_dwb_cnv()
89 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0); in dwb2_config_dwb_cnv()
93 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate); in dwb2_config_dwb_cnv()
96 REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc); in dwb2_config_dwb_cnv()
118 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); in dwb2_enable()
127 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb2_enable()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.c57 REG_UPDATE(DOMAIN1_PG_CONFIG, in dcn302_dpp_pg_control()
65 REG_UPDATE(DOMAIN3_PG_CONFIG, in dcn302_dpp_pg_control()
73 REG_UPDATE(DOMAIN5_PG_CONFIG, in dcn302_dpp_pg_control()
81 REG_UPDATE(DOMAIN7_PG_CONFIG, in dcn302_dpp_pg_control()
89 REG_UPDATE(DOMAIN9_PG_CONFIG, in dcn302_dpp_pg_control()
114 REG_UPDATE(DOMAIN0_PG_CONFIG, in dcn302_hubp_pg_control()
122 REG_UPDATE(DOMAIN2_PG_CONFIG, in dcn302_hubp_pg_control()
130 REG_UPDATE(DOMAIN4_PG_CONFIG, in dcn302_hubp_pg_control()
138 REG_UPDATE(DOMAIN6_PG_CONFIG, in dcn302_hubp_pg_control()
146 REG_UPDATE(DOMAIN8_PG_CONFIG, in dcn302_hubp_pg_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp.c79 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp401_dpp_setup()
80 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp401_dpp_setup()
81 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp401_dpp_setup()
82 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp401_dpp_setup()
84 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); in dpp401_dpp_setup()
85 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); in dpp401_dpp_setup()
86 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); in dpp401_dpp_setup()
184 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); in dpp401_dpp_setup()
185 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); in dpp401_dpp_setup()
186 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp401_dpp_setup()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c71 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp201_cnv_setup()
72 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp201_cnv_setup()
73 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp201_cnv_setup()
74 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp201_cnv_setup()
167 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); in dpp201_cnv_setup()
168 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); in dpp201_cnv_setup()
169 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp201_cnv_setup()
170 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); in dpp201_cnv_setup()
175 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp201_cnv_setup()
180 REG_UPDATE(CURSOR_CONTROL, in dpp201_cnv_setup()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c43 REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst], in dce_enable_fe_clock()
126 REG_UPDATE(BLND_CONTROL[blnd_inst], in dce_set_blender_mode()
141 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, in dce_disable_sram_shut_down()
149 REG_UPDATE(DCFEV_CLOCK_CONTROL, in dce_underlay_clock_enable()
180 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
190 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
201 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.c56 REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value); in dccg314_trigger_dio_fifo_resync()
164 REG_UPDATE(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
173 REG_UPDATE(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
182 REG_UPDATE(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
191 REG_UPDATE(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
224 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], in dccg314_set_dtbclk_dto()
238 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], in dccg314_set_dtbclk_dto()
342 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0); in dccg314_dpp_root_clock_control()
348 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 1); in dccg314_dpp_root_clock_control()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c67 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg2_update_dpp_dto()
70 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg2_update_dpp_dto()
104 REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, in dccg2_set_fifo_errdet_ovr_en()
116 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
128 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_drop_pixel()
181 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1); in dccg2_enable_memory_low_power()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/
H A Ddcn20_hubbub.c442 REG_UPDATE(DCN_VM_FB_LOCATION_TOP, in hubbub2_update_dchub()
445 REG_UPDATE(DCN_VM_FB_LOCATION_BASE, in hubbub2_update_dchub()
449 REG_UPDATE(DCN_VM_AGP_BASE, in hubbub2_update_dchub()
454 REG_UPDATE(DCN_VM_AGP_BOT, in hubbub2_update_dchub()
459 REG_UPDATE(DCN_VM_AGP_TOP, in hubbub2_update_dchub()
467 REG_UPDATE(DCN_VM_AGP_BASE, in hubbub2_update_dchub()
472 REG_UPDATE(DCN_VM_AGP_BOT, in hubbub2_update_dchub()
477 REG_UPDATE(DCN_VM_AGP_TOP, in hubbub2_update_dchub()
485 REG_UPDATE(DCN_VM_AGP_BASE, in hubbub2_update_dchub()
490 REG_UPDATE(DCN_VM_AGP_BOT, in hubbub2_update_dchub()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.c105 REG_UPDATE(DOMAIN16_PG_CONFIG, in pg_cntl35_dsc_pg_control()
113 REG_UPDATE(DOMAIN17_PG_CONFIG, in pg_cntl35_dsc_pg_control()
121 REG_UPDATE(DOMAIN18_PG_CONFIG, in pg_cntl35_dsc_pg_control()
129 REG_UPDATE(DOMAIN19_PG_CONFIG, in pg_cntl35_dsc_pg_control()
206 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hubp_dpp_pg_control()
211 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hubp_dpp_pg_control()
216 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hubp_dpp_pg_control()
221 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hubp_dpp_pg_control()
280 REG_UPDATE(DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hpo_pg_control()
328 REG_UPDATE(DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_io_clk_pg_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c186 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); in enable_phy_bypass_mode()
207 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); in disable_prbs_mode()
276 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); in set_link_training_complete()
492 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
496 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
506 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
548 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, in dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2()
558 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); in dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2()
580 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); in set_dp_phy_pattern_passthrough_mode()
656 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); in configure_encoder()
[all …]
H A Ddce_panel_cntl.c108 REG_UPDATE(PWRSEQ_REF_DIV, in dce_panel_cntl_hw_init()
136 REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1); in dce_panel_cntl_hw_init()
139 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, in dce_panel_cntl_hw_init()
242 REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit); in dce_driver_set_backlight()
245 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, in dce_driver_set_backlight()
H A Ddce_clock_source.c764 REG_UPDATE(RESYNC_CNTL, in dce110_program_pixel_clk_resync()
777 REG_UPDATE(RESYNC_CNTL, in dce110_program_pixel_clk_resync()
781 REG_UPDATE(RESYNC_CNTL, in dce110_program_pixel_clk_resync()
785 REG_UPDATE(RESYNC_CNTL, in dce110_program_pixel_clk_resync()
789 REG_UPDATE(RESYNC_CNTL, in dce110_program_pixel_clk_resync()
838 REG_UPDATE(PIXCLK_RESYNC_CNTL, in dce112_program_pixel_clk_resync()
1008 REG_UPDATE(PIXEL_RATE_CNTL[inst], in dcn31_program_pix_clk()
1013 REG_UPDATE(PIXEL_RATE_CNTL[inst], in dcn31_program_pix_clk()
1314 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0); in dcn20_override_dp_pix_clk()
1317 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); in dcn20_override_dp_pix_clk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_ddc.c148 REG_UPDATE(gpio.MASK_reg, in set_config()
153 REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1); in set_config()
157 REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1); in set_config()
167 REG_UPDATE(dc_gpio_aux_ctrl_5, in set_config()
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb_cm.c204 REG_UPDATE(DWB_OGAM_LUT_CONTROL, in dwb3_program_ogam_pwl()
214 REG_UPDATE(DWB_OGAM_LUT_CONTROL, in dwb3_program_ogam_pwl()
224 REG_UPDATE(DWB_OGAM_LUT_CONTROL, in dwb3_program_ogam_pwl()
267 REG_UPDATE(DWB_OGAM_CONTROL, DWB_OGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1); in dwb3_program_ogam_lut()
316 REG_UPDATE(DWB_GAMUT_REMAP_COEF_FORMAT, DWB_GAMUT_REMAP_COEF_FORMAT, coef_format); in dwb3_program_gamut_remap()
394 REG_UPDATE(DWB_HDR_MULT_COEF, DWB_HDR_MULT_COEF, params->hdr_mult); in dwb3_program_hdr_mult()
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_panel_cntl.c116 REG_UPDATE(PWRSEQ_REF_DIV, in dcn301_panel_cntl_hw_init()
139 REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1); in dcn301_panel_cntl_hw_init()
142 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, in dcn301_panel_cntl_hw_init()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn35/
H A Ddcn35_dsc.c103 REG_UPDATE(DSC_TOP_CONTROL, in dsc35_enable()
113 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable); in dsc35_set_fgcg()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c160 REG_UPDATE(DSC_TOP_CONTROL, in dsc401_enable()
181 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, in dsc401_disable()
184 REG_UPDATE(DSC_TOP_CONTROL, in dsc401_disable()
201 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, in dsc401_disconnect()
398 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable); in dsc401_set_fgcg()
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/
H A Ddcn35_mmhubbub.c58 REG_UPDATE(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, !enabled); in dcn35_mmhubbub_set_fgcg()
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn35/
H A Ddcn35_dwb.c56 REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_FGCG_REP_DIS, !enable); in dcn35_dwbc_set_fgcg()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/
H A Ddcn10_dio.c27 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); in dcn10_dio_mem_pwr_ctrl()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/
H A Ddcn201_hubbub.c70 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, in hubbub201_program_watermarks()

12