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Searched refs:REG_UPDATE (Results 1 – 25 of 70) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
H A Ddcn32_mmhubbub.c97 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1); in mmhubbub32_warmup_mcif()
100 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); in mmhubbub32_warmup_mcif()
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub32_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub32_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub32_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub32_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub32_config_mcif_buf()
119 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub32_config_mcif_buf()
122 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); in mmhubbub32_config_mcif_buf()
123 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub32_config_mcif_buf()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.c97 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1); in mmhubbub3_warmup_mcif()
100 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); in mmhubbub3_warmup_mcif()
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub3_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub3_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub3_config_mcif_buf()
119 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
122 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); in mmhubbub3_config_mcif_buf()
123 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
[all …]
H A Ddcn30_vpg.c79 REG_UPDATE(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, 1); in vpg3_update_generic_info_packet()
82 REG_UPDATE(VPG_GENERIC_PACKET_ACCESS_CTRL, in vpg3_update_generic_info_packet()
113 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
117 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
121 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
125 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
129 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
133 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
137 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
141 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
[all …]
H A Ddcn30_afmt.c56 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_hdmi_audio()
71 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); in afmt3_setup_hdmi_audio()
139 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); in afmt3_se_audio_setup()
143 REG_UPDATE(AFMT_MEM_PWR, AFMT_MEM_PWR_FORCE, 0); in afmt3_se_audio_setup()
156 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); in afmt3_audio_mute_control()
165 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_audio_info_immediate_update()
177 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_dp_audio()
186 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_setup_dp_audio()
189 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); in afmt3_setup_dp_audio()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c83 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1); in dwb2_config_dwb_cnv()
84 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x); in dwb2_config_dwb_cnv()
85 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y); in dwb2_config_dwb_cnv()
86 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb2_config_dwb_cnv()
87 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb2_config_dwb_cnv()
89 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0); in dwb2_config_dwb_cnv()
93 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate); in dwb2_config_dwb_cnv()
96 REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc); in dwb2_config_dwb_cnv()
118 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); in dwb2_enable()
127 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb2_enable()
[all …]
H A Ddcn20_dwb_scl.c754 REG_UPDATE(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, h_ratio_luma); in dwb_program_horz_scalar()
757 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, h_taps_luma - 1); in dwb_program_horz_scalar()
758 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, h_taps_chroma - 1); in dwb_program_horz_scalar()
780 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, h_init_phase_luma_int); in dwb_program_horz_scalar()
781 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, h_init_phase_luma_frac); in dwb_program_horz_scalar()
782 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, h_init_phase_chroma_int); in dwb_program_horz_scalar()
783 REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, h_init_phase_chroma_frac); in dwb_program_horz_scalar()
832 REG_UPDATE(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, v_ratio_luma); in dwb_program_vert_scalar()
835 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, v_taps_luma - 1); in dwb_program_vert_scalar()
836 REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, v_taps_chroma - 1); in dwb_program_vert_scalar()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.c147 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
150 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
153 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
156 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
246 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
250 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
254 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
258 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
262 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
283 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_symclk_fe_rcg()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb.c76 REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 1); in dwb3_config_fc()
77 REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_X, params->cnv_params.crop_x); in dwb3_config_fc()
78 REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_Y, params->cnv_params.crop_y); in dwb3_config_fc()
79 REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb3_config_fc()
80 REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb3_config_fc()
82 REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 0); in dwb3_config_fc()
86 REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_RATE, params->capture_rate); in dwb3_config_fc()
97 REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 1); in dwb3_enable()
111 REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb3_enable()
114 REG_UPDATE(FC_FLOW_CTRL, FC_FIRST_PIXEL_DELAY_COUNT, 96); in dwb3_enable()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c74 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in dce110_update_generic_info_packet()
94 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in dce110_update_generic_info_packet()
99 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet()
140 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
144 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
148 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
152 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
156 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
160 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
164 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
[all …]
H A Ddce_dmcu.c113 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); in dce_get_dmcu_psr_state()
126 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); in dce_get_dmcu_psr_state()
145 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
148 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
152 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_dmcu_set_psr_enable()
195 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
199 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
203 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
207 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
224 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
[all …]
H A Ddce_ipp.c49 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_position()
53 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); in dce_ipp_cursor_set_position()
64 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_position()
75 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_attributes()
134 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_attributes()
144 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
160 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
164 REG_UPDATE(INPUT_GAMMA_CONTROL, in dce_ipp_program_prescale()
184 REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); in dce_ipp_program_input_lut()
213 REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_ipp_program_input_lut()
[all …]
H A Ddce_mem_input.c150 REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, in dce_mi_program_pte_vm()
169 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_urgency_watermark()
184 REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL3, in dce60_program_urgency_watermark()
199 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in dce120_program_urgency_watermark()
218 REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, in dce60_program_nbp_watermark()
226 REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, in dce60_program_nbp_watermark()
237 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_nbp_watermark()
245 REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, in program_nbp_watermark()
250 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, in program_nbp_watermark()
258 REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL, in program_nbp_watermark()
[all …]
H A Ddce_abm.c78 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_abm_set_pipe()
110 REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_pwm_u16_16); in dmcu_set_backlight_level()
118 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); in dmcu_set_backlight_level()
121 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dmcu_set_backlight_level()
158 REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL, in dce_abm_init()
161 REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL, in dce_abm_init()
164 REG_UPDATE(BL1_PWM_USER_LEVEL, in dce_abm_init()
215 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_abm_set_level()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
H A Ddcn401_dccg.c63 REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable); in dcn401_set_dppclk_enable()
66 REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable); in dcn401_set_dppclk_enable()
69 REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable); in dcn401_set_dppclk_enable()
72 REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable); in dcn401_set_dppclk_enable()
183 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg401_set_pixel_rate_div()
189 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg401_set_pixel_rate_div()
195 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg401_set_pixel_rate_div()
201 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg401_set_pixel_rate_div()
227 REG_UPDATE(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
236 REG_UPDATE(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.c57 REG_UPDATE(DOMAIN1_PG_CONFIG, in dcn302_dpp_pg_control()
65 REG_UPDATE(DOMAIN3_PG_CONFIG, in dcn302_dpp_pg_control()
73 REG_UPDATE(DOMAIN5_PG_CONFIG, in dcn302_dpp_pg_control()
81 REG_UPDATE(DOMAIN7_PG_CONFIG, in dcn302_dpp_pg_control()
89 REG_UPDATE(DOMAIN9_PG_CONFIG, in dcn302_dpp_pg_control()
114 REG_UPDATE(DOMAIN0_PG_CONFIG, in dcn302_hubp_pg_control()
122 REG_UPDATE(DOMAIN2_PG_CONFIG, in dcn302_hubp_pg_control()
130 REG_UPDATE(DOMAIN4_PG_CONFIG, in dcn302_hubp_pg_control()
138 REG_UPDATE(DOMAIN6_PG_CONFIG, in dcn302_hubp_pg_control()
146 REG_UPDATE(DOMAIN8_PG_CONFIG, in dcn302_hubp_pg_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp.c83 REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0); in dpp2_power_on_obuf()
85 REG_UPDATE(OBUF_MEM_PWR_CTRL, in dpp2_power_on_obuf()
88 REG_UPDATE(DSCL_MEM_PWR_CTRL, in dpp2_power_on_obuf()
124 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
125 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
126 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
127 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
221 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); in dpp2_cnv_setup()
222 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); in dpp2_cnv_setup()
223 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp2_cnv_setup()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_gpio.c54 REG_UPDATE(MASK_reg, MASK, gpio->store.mask); in restore_registers()
55 REG_UPDATE(A_reg, A, gpio->store.a); in restore_registers()
56 REG_UPDATE(EN_reg, EN, gpio->store.en); in restore_registers()
107 REG_UPDATE(A_reg, A, value); in dal_hw_gpio_set_value()
114 REG_UPDATE(EN_reg, EN, ~value); in dal_hw_gpio_set_value()
151 REG_UPDATE(EN_reg, EN, 0); in dal_hw_gpio_config_mode()
152 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
157 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
158 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
163 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c75 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg31_update_dpp_dto()
78 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg31_update_dpp_dto()
105 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
109 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
113 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
117 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
141 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
145 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
149 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
153 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.c59 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, in optc2_enable_crtc()
63 REG_UPDATE(CONTROL, in optc2_enable_crtc()
114 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
117 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
120 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
139 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, in optc2_set_dsc_config()
145 REG_UPDATE(OPTC_WIDTH_CONTROL, in optc2_set_dsc_config()
174 REG_UPDATE(OTG_H_TIMING_CNTL, in optc2_set_odm_bypass()
213 REG_UPDATE(OPTC_WIDTH_CONTROL, in optc2_set_odm_combine()
249 REG_UPDATE(DWB_SOURCE_SELECT, in optc2_set_dwb_source()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_apg.c53 REG_UPDATE(APG_CONTROL, APG_RESET, 1); in apg31_enable()
57 REG_UPDATE(APG_CONTROL, APG_RESET, 0); in apg31_enable()
63 REG_UPDATE(APG_CONTROL2, APG_ENABLE, 1); in apg31_enable()
72 REG_UPDATE(APG_CONTROL2, APG_ENABLE, 0); in apg31_disable()
88 REG_UPDATE(APG_CONTROL2, APG_DP_AUDIO_STREAM_ID, 0); in apg31_se_audio_setup()
92 REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 0xFF); in apg31_se_audio_setup()
95 REG_UPDATE(APG_MEM_PWR, APG_MEM_PWR_FORCE, 0); in apg31_se_audio_setup()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c74 REG_UPDATE(DCHUBP_CNTL, in hubp1_disconnect()
77 REG_UPDATE(CURSOR_CONTROL, in hubp1_disconnect()
86 REG_UPDATE(DCHUBP_CNTL, in hubp1_disable_control()
107 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); in hubp1_clear_underflow()
115 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); in hubp1_set_hubp_blank_en()
262 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
266 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
271 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
277 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
282 REG_UPDATE(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp.c79 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp401_dpp_setup()
80 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp401_dpp_setup()
81 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp401_dpp_setup()
82 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp401_dpp_setup()
84 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); in dpp401_dpp_setup()
85 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); in dpp401_dpp_setup()
86 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); in dpp401_dpp_setup()
184 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); in dpp401_dpp_setup()
185 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); in dpp401_dpp_setup()
186 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp401_dpp_setup()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c71 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp201_cnv_setup()
72 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp201_cnv_setup()
73 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp201_cnv_setup()
74 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp201_cnv_setup()
167 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); in dpp201_cnv_setup()
168 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); in dpp201_cnv_setup()
169 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp201_cnv_setup()
170 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); in dpp201_cnv_setup()
175 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp201_cnv_setup()
180 REG_UPDATE(CURSOR_CONTROL, in dpp201_cnv_setup()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c48 REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address.lut3d.addr.high_part); in hubp401_program_3dlut_fl_addr()
56 REG_UPDATE(HUBP_3DLUT_DLG_PARAM, REFCYC_PER_3DLUT_GROUP, refcyc_per_3dlut_group); in hubp401_program_3dlut_fl_dlg_param()
63 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, enable ? 1 : 0); in hubp401_enable_3dlut_fl()
79 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, addr_mode); in hubp401_program_3dlut_fl_addressing_mode()
86 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, width); in hubp401_program_3dlut_fl_width()
93 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, protection_bits); in hubp401_program_3dlut_fl_tmz_protected()
120 REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mode); in hubp401_program_3dlut_fl_mode()
127 REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format); in hubp401_program_3dlut_fl_format()
150 REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, in hubp401_program_3dlut_fl_config()
152 REG_UPDATE(HUBP_3DLUT_ADDRESS_LOW, in hubp401_program_3dlut_fl_config()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c43 REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst], in dce_enable_fe_clock()
126 REG_UPDATE(BLND_CONTROL[blnd_inst], in dce_set_blender_mode()
141 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, in dce_disable_sram_shut_down()
149 REG_UPDATE(DCFEV_CLOCK_CONTROL, in dce_underlay_clock_enable()
180 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
190 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
201 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()

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