Home
last modified time | relevance | path

Searched refs:REG_UPDATE (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_vpg.c79 REG_UPDATE(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, 1); in vpg3_update_generic_info_packet()
82 REG_UPDATE(VPG_GENERIC_PACKET_ACCESS_CTRL, in vpg3_update_generic_info_packet()
113 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
117 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
121 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
125 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
129 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
133 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
137 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
141 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
[all …]
H A Ddcn30_mmhubbub.c97 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1); in mmhubbub3_warmup_mcif()
100 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); in mmhubbub3_warmup_mcif()
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub3_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub3_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub3_config_mcif_buf()
119 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
122 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); in mmhubbub3_config_mcif_buf()
123 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
[all …]
H A Ddcn30_afmt.c56 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_hdmi_audio()
71 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); in afmt3_setup_hdmi_audio()
139 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); in afmt3_se_audio_setup()
143 REG_UPDATE(AFMT_MEM_PWR, AFMT_MEM_PWR_FORCE, 0); in afmt3_se_audio_setup()
156 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); in afmt3_audio_mute_control()
165 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_audio_info_immediate_update()
177 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_dp_audio()
186 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_setup_dp_audio()
189 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); in afmt3_setup_dp_audio()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c83 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1); in dwb2_config_dwb_cnv()
84 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x); in dwb2_config_dwb_cnv()
85 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y); in dwb2_config_dwb_cnv()
86 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb2_config_dwb_cnv()
87 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb2_config_dwb_cnv()
89 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0); in dwb2_config_dwb_cnv()
93 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate); in dwb2_config_dwb_cnv()
96 REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc); in dwb2_config_dwb_cnv()
118 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); in dwb2_enable()
127 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb2_enable()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c74 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in dce110_update_generic_info_packet()
94 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in dce110_update_generic_info_packet()
99 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet()
140 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
144 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
148 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
152 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
156 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
160 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
164 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn42/
H A Ddcn42_dccg.c33 REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, in dccg42_otg_add_pixel()
37 REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, in dccg42_otg_add_pixel()
41 REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, in dccg42_otg_add_pixel()
45 REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, in dccg42_otg_add_pixel()
60 REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, in dccg42_otg_drop_pixel()
64 REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, in dccg42_otg_drop_pixel()
68 REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, in dccg42_otg_drop_pixel()
72 REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, in dccg42_otg_drop_pixel()
90 REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !enable); in dccg42_enable_global_fgcg()
113 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg42_set_physymclk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.c57 REG_UPDATE(DOMAIN1_PG_CONFIG, in dcn302_dpp_pg_control()
65 REG_UPDATE(DOMAIN3_PG_CONFIG, in dcn302_dpp_pg_control()
73 REG_UPDATE(DOMAIN5_PG_CONFIG, in dcn302_dpp_pg_control()
81 REG_UPDATE(DOMAIN7_PG_CONFIG, in dcn302_dpp_pg_control()
89 REG_UPDATE(DOMAIN9_PG_CONFIG, in dcn302_dpp_pg_control()
114 REG_UPDATE(DOMAIN0_PG_CONFIG, in dcn302_hubp_pg_control()
122 REG_UPDATE(DOMAIN2_PG_CONFIG, in dcn302_hubp_pg_control()
130 REG_UPDATE(DOMAIN4_PG_CONFIG, in dcn302_hubp_pg_control()
138 REG_UPDATE(DOMAIN6_PG_CONFIG, in dcn302_hubp_pg_control()
146 REG_UPDATE(DOMAIN8_PG_CONFIG, in dcn302_hubp_pg_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn60/
H A Ddcn60_dccg.c51 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg60_set_pixel_rate_div()
55 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg60_set_pixel_rate_div()
59 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg60_set_pixel_rate_div()
63 REG_UPDATE(OTG_PIXEL_RATE_DIV, in dccg60_set_pixel_rate_div()
81 REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 1); in dccg60_set_dto_dscclk()
89 REG_UPDATE(DSCCLK_SRC_SEL, DSCCLK0_SRC_SEL, 1); in dccg60_set_dto_dscclk()
91 REG_UPDATE(DSCCLK_SRC_SEL, DSCCLK0_SRC_SEL, 0); in dccg60_set_dto_dscclk()
97 REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1); in dccg60_set_dto_dscclk()
100 REG_UPDATE(DSCCLK_SRC_SEL, DSCCLK1_SRC_SEL, 1); in dccg60_set_dto_dscclk()
102 REG_UPDATE(DSCCLK_SRC_SEL, DSCCLK1_SRC_SEL, 0); in dccg60_set_dto_dscclk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_ddc.c148 REG_UPDATE(gpio.MASK_reg, in set_config()
153 REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1); in set_config()
157 REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1); in set_config()
167 REG_UPDATE(dc_gpio_aux_ctrl_5, in set_config()
276 REG_UPDATE(dc_i3cpad_control0, DC_I3CPAD_DDCDATA_MASK, ddc->base.store.mask); in restore_registers_ddc_i3cpad()
277 REG_UPDATE(dc_i3cpad_control0, DC_I3CPAD_DATA_A, ddc->base.store.a); in restore_registers_ddc_i3cpad()
278 REG_UPDATE(dc_i3cpad_control0, DC_I3CPAD_DATA_EN, ddc->base.store.en); in restore_registers_ddc_i3cpad()
281 REG_UPDATE(dc_i3cpad_control0, DC_I3CPAD_DDCCLK_MASK, ddc->base.store.mask); in restore_registers_ddc_i3cpad()
282 REG_UPDATE(dc_i3cpad_control0, DC_I3CPAD_CLK_A, ddc->base.store.a); in restore_registers_ddc_i3cpad()
283 REG_UPDATE(dc_i3cpad_control0, DC_I3CPAD_CLK_EN, ddc->base.store.en); in restore_registers_ddc_i3cpad()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c71 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp201_cnv_setup()
72 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp201_cnv_setup()
73 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp201_cnv_setup()
74 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp201_cnv_setup()
167 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); in dpp201_cnv_setup()
168 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); in dpp201_cnv_setup()
169 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp201_cnv_setup()
170 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); in dpp201_cnv_setup()
175 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp201_cnv_setup()
180 REG_UPDATE(CURSOR_CONTROL, in dpp201_cnv_setup()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c43 REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst], in dce_enable_fe_clock()
126 REG_UPDATE(BLND_CONTROL[blnd_inst], in dce_set_blender_mode()
141 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, in dce_disable_sram_shut_down()
149 REG_UPDATE(DCFEV_CLOCK_CONTROL, in dce_underlay_clock_enable()
180 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
190 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
201 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn42/
H A Ddcn42_pg_cntl.c46 REG_UPDATE(DMU_CLK_CNTL, LONO_FGCG_REP_DIS, 1); in pg_cntl42_save_and_disable_global_fgcg_rep()
49 REG_UPDATE(AZ_CLOCK_CNTL, AZ_GLOBAL_FGCG_REP_DIS, 1); in pg_cntl42_save_and_disable_global_fgcg_rep()
58 REG_UPDATE(DMU_CLK_CNTL, LONO_FGCG_REP_DIS, state->dmu_rep_fgcg); in pg_cntl42_restore_global_fgcg_rep()
61 REG_UPDATE(AZ_CLOCK_CNTL, AZ_GLOBAL_FGCG_REP_DIS, state->az_rep_fgcg); in pg_cntl42_restore_global_fgcg_rep()
130 REG_UPDATE(DOMAIN16_PG_CONFIG, in pg_cntl42_dsc_pg_control()
138 REG_UPDATE(DOMAIN17_PG_CONFIG, in pg_cntl42_dsc_pg_control()
146 REG_UPDATE(DOMAIN18_PG_CONFIG, in pg_cntl42_dsc_pg_control()
154 REG_UPDATE(DOMAIN19_PG_CONFIG, in pg_cntl42_dsc_pg_control()
231 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl42_hubp_dpp_pg_control()
236 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl42_hubp_dpp_pg_control()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c67 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg2_update_dpp_dto()
70 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg2_update_dpp_dto()
104 REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, in dccg2_set_fifo_errdet_ovr_en()
116 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
128 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_drop_pixel()
181 REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1); in dccg2_enable_memory_low_power()
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dbios_parser_helper.c73 REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, state); in bios_set_scratch_acc_mode_change()
82 REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state); in bios_set_scratch_critical_state()
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_panel_cntl.c116 REG_UPDATE(PWRSEQ_REF_DIV, in dcn301_panel_cntl_hw_init()
139 REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1); in dcn301_panel_cntl_hw_init()
142 REG_UPDATE(BL_PWM_GRP1_REG_LOCK, in dcn301_panel_cntl_hw_init()
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/
H A Ddcn35_mmhubbub.c58 REG_UPDATE(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, !enabled); in dcn35_mmhubbub_set_fgcg()
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn35/
H A Ddcn35_dwb.c56 REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_FGCG_REP_DIS, !enable); in dcn35_dwbc_set_fgcg()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/
H A Ddcn10_dio.c27 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); in dcn10_dio_mem_pwr_ctrl()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/
H A Ddcn201_hubbub.c70 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, in hubbub201_program_watermarks()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c92 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg21_update_dpp_dto()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
H A Ddcn201_hubp.c71 REG_UPDATE(HUBPRET_CONTROL, in hubp201_program_requestor()
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h88 #define REG_UPDATE(reg_name, field, val) \ macro
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/
H A Ddcn50_hwseq.c499 REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, enable); in dcn50_setup_hpo_hw_control()
568 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); in dcn50_init_hw()
724 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); in dcn50_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c676 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); in dcn30_init_hw()
688 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); in dcn30_init_hw()
816 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); in dcn30_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/
H A Ddcn60_hwseq.c572 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); in dcn60_init_hw()
736 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); in dcn60_init_hw()