Searched refs:REG_SET_4 (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| H A D | dcn401_dsc.c | 232 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, in dsc_write_to_registers()
245 REG_SET_4(DSCC_INTERRUPT_CONTROL0, 0, in dsc_write_to_registers()
314 REG_SET_4(DSCC_PPS_CONFIG12, 0, in dsc_write_to_registers()
320 REG_SET_4(DSCC_PPS_CONFIG13, 0, in dsc_write_to_registers()
326 REG_SET_4(DSCC_PPS_CONFIG14, 0, in dsc_write_to_registers()
|
| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.c | 613 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, in dsc_write_to_registers()
626 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, in dsc_write_to_registers()
695 REG_SET_4(DSCC_PPS_CONFIG12, 0, in dsc_write_to_registers()
701 REG_SET_4(DSCC_PPS_CONFIG13, 0, in dsc_write_to_registers()
707 REG_SET_4(DSCC_PPS_CONFIG14, 0, in dsc_write_to_registers()
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_vpg.c | 88 REG_SET_4(VPG_GENERIC_PACKET_DATA, 0, in vpg3_update_generic_info_packet()
|
| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| H A D | dcn201_hubp.c | 74 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp201_program_requestor()
|
| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_reg.h | 76 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ macro
|