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Searched refs:REG_SET_4 (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c660 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp20_program_shaper_luta_settings()
667 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp20_program_shaper_luta_settings()
674 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp20_program_shaper_luta_settings()
681 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp20_program_shaper_luta_settings()
688 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp20_program_shaper_luta_settings()
695 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp20_program_shaper_luta_settings()
702 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, in dpp20_program_shaper_luta_settings()
709 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, in dpp20_program_shaper_luta_settings()
716 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, in dpp20_program_shaper_luta_settings()
723 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, in dpp20_program_shaper_luta_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
H A Ddcn32_mpc.c373 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
380 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
387 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
394 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
401 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
408 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
415 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
422 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
430 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
437 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c942 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp3_program_shaper_luta_settings()
949 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp3_program_shaper_luta_settings()
956 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp3_program_shaper_luta_settings()
963 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp3_program_shaper_luta_settings()
970 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp3_program_shaper_luta_settings()
977 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp3_program_shaper_luta_settings()
984 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, in dpp3_program_shaper_luta_settings()
991 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, in dpp3_program_shaper_luta_settings()
998 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, in dpp3_program_shaper_luta_settings()
1005 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, in dpp3_program_shaper_luta_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_transform.c252 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in program_multi_taps_filter()
1506 REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, in regamma_config_regions_and_segments()
1513 REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, in regamma_config_regions_and_segments()
1520 REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, in regamma_config_regions_and_segments()
1527 REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, in regamma_config_regions_and_segments()
1534 REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, in regamma_config_regions_and_segments()
1541 REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, in regamma_config_regions_and_segments()
1548 REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, in regamma_config_regions_and_segments()
1555 REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, in regamma_config_regions_and_segments()
H A Ddce_stream_encoder.c106 REG_SET_4(AFMT_GENERIC_HDR, 0, in dce110_update_generic_info_packet()
483 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, in dce110_stream_encoder_dp_set_stream_attribute()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_vpg.c88 REG_SET_4(VPG_GENERIC_PACKET_DATA, 0, in vpg3_update_generic_info_packet()
H A Ddcn30_cm_common.c92 REG_SET_4(reg_region_cur, 0, in cm_helper_program_gamcor_xfer_func()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
H A Ddcn201_hubp.c74 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp201_program_requestor()
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h76 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ macro
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_dscl.c264 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in dpp1_dscl_set_scaler_filter()
688 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp1_dscl_set_scaler_manual_scale()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb_scl.c709 REG_SET_4(WBSCL_COEF_RAM_TAP_DATA, 0, in wbscl_set_scaler_filter()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_cm_common.c135 REG_SET_4(reg_region_cur, 0, in cm_helper_program_xfer_func()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c228 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp401_program_requestor()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c581 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp1_program_requestor()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c204 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp2_program_requestor()