| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| H A D | dcn401_dpp_dscl.c | 253 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0, in dpp401_dscl_set_scaler_filter()
674 REG_SET_3(DSCL_EASF_V_MODE, 0, in dpp401_dscl_program_easf_v()
717 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG0, 0, in dpp401_dscl_program_easf_v()
721 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG1, 0, in dpp401_dscl_program_easf_v()
725 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG2, 0, in dpp401_dscl_program_easf_v()
729 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG3, 0, in dpp401_dscl_program_easf_v()
733 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG4, 0, in dpp401_dscl_program_easf_v()
737 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG5, 0, in dpp401_dscl_program_easf_v()
741 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG6, 0, in dpp401_dscl_program_easf_v()
749 REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG0, 0, in dpp401_dscl_program_easf_v()
[all …]
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| H A D | dcn401_dpp_cm.c | 100 REG_SET_3(FORMAT_CONTROL, 0, in dpp401_full_bypass()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_ipp.c | 102 REG_SET_3(CUR_COLOR1, 0, in dce_ipp_cursor_set_attributes()
107 REG_SET_3(CUR_COLOR2, 0, in dce_ipp_cursor_set_attributes()
187 REG_SET_3(DC_LUT_CONTROL, 0, in dce_ipp_program_input_lut()
226 REG_SET_3(DEGAMMA_CONTROL, 0, in dce_ipp_set_degamma()
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| H A D | dce_abm.c | 148 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, in dce_abm_init()
153 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, in dce_abm_init()
171 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, in dce_abm_init()
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| H A D | dmub_abm_lcd.c | 88 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, in dmub_abm_init()
93 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, in dmub_abm_init()
111 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, in dmub_abm_init()
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| H A D | dce_i2c_hw.c | 107 REG_SET_3(DC_I2C_DATA, 0, in process_channel_reply()
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| /linux/drivers/gpu/drm/amd/display/dc/opp/dcn20/ |
| H A D | dcn20_opp.c | 224 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
235 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
246 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| H A D | dcn401_dsc.c | 246 REG_SET_3(DSCC_CONFIG0, 0, in dsc_write_to_registers()
270 REG_SET_3(DSCC_PPS_CONFIG0, 0, in dsc_write_to_registers()
304 REG_SET_3(DSCC_PPS_CONFIG6, 0, in dsc_write_to_registers()
321 REG_SET_3(DSCC_PPS_CONFIG10, 0, in dsc_write_to_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
| H A D | dcn20_optc.c | 167 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_bypass()
208 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_combine()
430 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc2_lock_doublebuffer_enable()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.c | 606 REG_SET_3(DSCC_CONFIG0, 0, in dsc_write_to_registers()
630 REG_SET_3(DSCC_PPS_CONFIG0, 0, in dsc_write_to_registers()
664 REG_SET_3(DSCC_PPS_CONFIG6, 0, in dsc_write_to_registers()
681 REG_SET_3(DSCC_PPS_CONFIG10, 0, in dsc_write_to_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/ |
| H A D | dcn401_optc.c | 117 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc401_set_odm_combine()
437 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc401_set_vupdate_keepout()
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| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_reg.h | 70 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ macro
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp.c | 304 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
310 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
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| H A D | dcn10_dpp_dscl.c | 251 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0, in dpp1_dscl_set_scaler_filter()
636 REG_SET_3(DSCL_AUTOCAL, 0, in dpp1_dscl_set_scaler_manual_scale()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/ |
| H A D | dcn314_optc.c | 84 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc314_set_odm_combine()
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| /linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/ |
| H A D | dcn32_mmhubbub.c | 89 REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true, in mmhubbub32_warmup_mcif()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_mmhubbub.c | 89 REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true, in mmhubbub3_warmup_mcif()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/ |
| H A D | dcn31_optc.c | 72 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc31_set_odm_combine()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| H A D | dcn401_hubp.c | 272 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp401_program_deadline()
277 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp401_program_deadline()
282 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp401_program_deadline()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| H A D | dcn10_optc.c | 585 REG_SET_3(OTG_BLACK_COLOR, 0, in optc1_program_blank_color()
762 REG_SET_3(OTG_TRIGA_CNTL, 0, in optc1_enable_reset_trigger()
771 REG_SET_3(OTG_TRIGA_CNTL, 0, in optc1_enable_reset_trigger()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| H A D | dcn10_hubp.c | 658 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp1_program_deadline()
663 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp1_program_deadline()
668 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp1_program_deadline()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| H A D | dcn20_hubp.c | 153 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp2_program_deadline()
158 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp2_program_deadline()
163 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp2_program_deadline()
684 REG_SET_3(DMDATA_QOS_CNTL, 0, in hubp2_dmdata_set_attributes()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/ |
| H A D | dcn35_optc.c | 92 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc35_set_odm_combine()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dwb_scl.c | 704 REG_SET_3(WBSCL_COEF_RAM_SELECT, 0, in wbscl_set_scaler_filter()
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| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| H A D | dcn10_link_encoder.c | 143 REG_SET_3(DP_DPHY_SYM0, 0, in program_pattern_symbols()
151 REG_SET_3(DP_DPHY_SYM1, 0, in program_pattern_symbols()
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