| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| H A D | dcn401_dsc.c | 214 REG_SET_2(DSCCIF_CONFIG0, 0, in dsc_write_to_registers()
270 REG_SET_2(DSCC_PPS_CONFIG2, 0, in dsc_write_to_registers()
274 REG_SET_2(DSCC_PPS_CONFIG3, 0, in dsc_write_to_registers()
281 REG_SET_2(DSCC_PPS_CONFIG5, 0, in dsc_write_to_registers()
290 REG_SET_2(DSCC_PPS_CONFIG7, 0, in dsc_write_to_registers()
294 REG_SET_2(DSCC_PPS_CONFIG8, 0, in dsc_write_to_registers()
298 REG_SET_2(DSCC_PPS_CONFIG9, 0, in dsc_write_to_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| H A D | dcn401_dpp.c | 75 REG_SET_2(FORMAT_CONTROL, 0, in dpp401_dpp_setup()
190 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp401_dpp_setup()
195 REG_SET_2(PRE_DEALPHA, 0, in dpp401_dpp_setup()
198 REG_SET_2(PRE_REALPHA, 0, in dpp401_dpp_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| H A D | dce_hwseq.c | 71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.c | 602 REG_SET_2(DSCCIF_CONFIG1, 0, in dsc_write_to_registers()
651 REG_SET_2(DSCC_PPS_CONFIG2, 0, in dsc_write_to_registers()
655 REG_SET_2(DSCC_PPS_CONFIG3, 0, in dsc_write_to_registers()
662 REG_SET_2(DSCC_PPS_CONFIG5, 0, in dsc_write_to_registers()
671 REG_SET_2(DSCC_PPS_CONFIG7, 0, in dsc_write_to_registers()
675 REG_SET_2(DSCC_PPS_CONFIG8, 0, in dsc_write_to_registers()
679 REG_SET_2(DSCC_PPS_CONFIG9, 0, in dsc_write_to_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_vmid.c | 88 REG_SET_2(CNTL, 0, in dcn20_vmid_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 88 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg21_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.c | 343 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg314_dpp_root_clock_control()
349 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg314_dpp_root_clock_control()
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| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_reg.h | 65 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ macro
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 64 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg2_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/ |
| H A D | hw_ddc.c | 101 REG_SET_2(gpio.MASK_reg, regval, in set_config()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 60 REG_SET_2(FORMAT_CONTROL, 0, in dpp201_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_link_encoder.c | 233 REG_SET_2(DP_DPHY_SYM2, 0, in program_pattern_symbols()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 169 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); in dcn401_init_hw()
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