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Searched refs:REG_SET_2 (Results 1 – 25 of 38) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_opp.c367 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
375 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
380 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
385 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
391 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
396 REG_SET_2(FMT_CLAMP_COMPONENT_R, 0, in dce110_opp_set_clamping()
400 REG_SET_2(FMT_CLAMP_COMPONENT_G, 0, in dce110_opp_set_clamping()
404 REG_SET_2(FMT_CLAMP_COMPONENT_B, 0, in dce110_opp_set_clamping()
427 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce60_opp_set_clamping()
435 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce60_opp_set_clamping()
[all …]
H A Ddce_transform.c131 REG_SET_2(SCL_TAP_CONTROL, 0, in setup_scaling_configuration()
167 REG_SET_2(SCL_TAP_CONTROL, 0, in dce60_setup_scaling_configuration()
202 REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0, in program_overscan()
205 REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0, in program_overscan()
269 REG_SET_2(VIEWPORT_START, 0, in program_viewport()
273 REG_SET_2(VIEWPORT_SIZE, 0, in program_viewport()
353 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in program_scl_ratios_inits()
357 REG_SET_2(SCL_VERT_FILTER_INIT, 0, in program_scl_ratios_inits()
377 REG_SET_2(SCL_HORZ_FILTER_INIT_RGB_LUMA, 0, in dce60_program_scl_ratios_inits()
382 REG_SET_2(SCL_HORZ_FILTER_INIT_CHROMA, 0, in dce60_program_scl_ratios_inits()
[all …]
H A Ddce_ipp.c55 REG_SET_2(CUR_POSITION, 0, in dce_ipp_cursor_set_position()
59 REG_SET_2(CUR_HOT_SPOT, 0, in dce_ipp_cursor_set_position()
117 REG_SET_2(CUR_SIZE, 0, in dce_ipp_cursor_set_attributes()
147 REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, in dce_ipp_program_prescale()
151 REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, in dce_ipp_program_prescale()
155 REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, in dce_ipp_program_prescale()
242 REG_SET_2(DEGAMMA_CONTROL, 0, in dce60_ipp_set_degamma()
H A Ddce_mem_input.c172 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in program_urgency_watermark()
187 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in dce60_program_urgency_watermark()
202 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in dce120_program_urgency_watermark()
206 REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0, in dce120_program_urgency_watermark()
575 REG_SET_2(GRPH_SWAP_CNTL, 0, in program_grph_pixel_format()
823 REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0, in program_sec_addr()
H A Ddce_stream_encoder.c453 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, in dce110_stream_encoder_dp_set_stream_attribute()
478 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, in dce110_stream_encoder_dp_set_stream_attribute()
495 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, in dce110_stream_encoder_dp_set_stream_attribute()
711 REG_SET_2(DP_MSE_RATE_CNTL, 0, in dce110_stream_encoder_set_throttled_vcp_size()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_dscl.c202 REG_SET_2(LB_DATA_FORMAT, 0, in dpp1_dscl_set_lb()
210 REG_SET_2(LB_MEMORY_CTRL, 0, in dpp1_dscl_set_lb()
368 REG_SET_2(SCL_MODE, scl_mode, in dpp1_dscl_set_scl_filter()
533 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in dpp1_dscl_set_manual_ratio_init()
539 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0, in dpp1_dscl_set_manual_ratio_init()
545 REG_SET_2(SCL_VERT_FILTER_INIT, 0, in dpp1_dscl_set_manual_ratio_init()
554 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, in dpp1_dscl_set_manual_ratio_init()
561 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0, in dpp1_dscl_set_manual_ratio_init()
570 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, in dpp1_dscl_set_manual_ratio_init()
590 REG_SET_2(RECOUT_START, 0, in dpp1_dscl_set_recout()
[all …]
H A Ddcn10_dpp_cm.c571 REG_SET_2(CM_BNS_VALUES_R, 0, in dpp1_program_bias_and_scale()
575 REG_SET_2(CM_BNS_VALUES_G, 0, in dpp1_program_bias_and_scale()
579 REG_SET_2(CM_BNS_VALUES_B, 0, in dpp1_program_bias_and_scale()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c615 REG_SET_2(BLANK_OFFSET_0, 0, in hubp1_program_deadline()
625 REG_SET_2(DST_AFTER_SCALER, 0, in hubp1_program_deadline()
650 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp1_program_deadline()
672 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp1_program_deadline()
717 REG_SET_2(PREFETCH_SETTINS, 0, in hubp1_setup_interdependent()
724 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp1_setup_interdependent()
734 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp1_setup_interdependent()
747 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp1_setup_interdependent()
795 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_system_aperture_settings()
835 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_context0_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c259 REG_SET_2(BLANK_OFFSET_0, 0, in hubp401_program_deadline()
269 REG_SET_2(DST_AFTER_SCALER, 0, in hubp401_program_deadline()
294 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp401_program_deadline()
316 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp401_program_deadline()
366 REG_SET_2(PREFETCH_SETTINGS, 0, in hubp401_setup_interdependent()
373 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp401_setup_interdependent()
377 REG_SET_2(FLIP_PARAMETERS_0, 0, in hubp401_setup_interdependent()
390 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp401_setup_interdependent()
403 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp401_setup_interdependent()
655 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, in hubp401_set_viewport()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c215 REG_SET_2(PRE_DEGAM, 0, in dpp3_set_pre_degam()
241 REG_SET_2(FORMAT_CONTROL, 0, in dpp3_cnv_setup()
360 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp3_cnv_setup()
365 REG_SET_2(PRE_DEALPHA, 0, in dpp3_cnv_setup()
368 REG_SET_2(PRE_REALPHA, 0, in dpp3_cnv_setup()
919 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, in dpp3_program_shaper_luta_settings()
922 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, in dpp3_program_shaper_luta_settings()
925 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, in dpp3_program_shaper_luta_settings()
929 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, in dpp3_program_shaper_luta_settings()
933 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, in dpp3_program_shaper_luta_settings()
[all …]
H A Ddcn30_dpp_cm.c151 REG_SET_2(CM_DEALPHA, 0, in dpp3_program_cm_dealpha()
163 REG_SET_2(CM_BIAS_Y_G_CB_B, 0, in dpp3_program_cm_bias()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c637 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, in dpp20_program_shaper_luta_settings()
640 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, in dpp20_program_shaper_luta_settings()
643 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, in dpp20_program_shaper_luta_settings()
647 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, in dpp20_program_shaper_luta_settings()
651 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, in dpp20_program_shaper_luta_settings()
655 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, in dpp20_program_shaper_luta_settings()
787 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, in dpp20_program_shaper_lutb_settings()
790 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, in dpp20_program_shaper_lutb_settings()
793 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, in dpp20_program_shaper_lutb_settings()
797 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, in dpp20_program_shaper_lutb_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
H A Ddcn32_mpc.c351 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
354 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
357 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
361 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
364 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
367 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
503 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
506 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
509 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
513 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_cm_common.c51 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_gamcor_xfer_func()
54 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_gamcor_xfer_func()
57 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_gamcor_xfer_func()
75 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_gamcor_xfer_func()
78 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_gamcor_xfer_func()
81 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_gamcor_xfer_func()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp.c75 REG_SET_2(FORMAT_CONTROL, 0, in dpp401_dpp_setup()
190 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp401_dpp_setup()
195 REG_SET_2(PRE_DEALPHA, 0, in dpp401_dpp_setup()
198 REG_SET_2(PRE_REALPHA, 0, in dpp401_dpp_setup()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_cm_common.c56 REG_SET_2(cur_csc_reg, 0, in cm_helper_program_color_matrices()
93 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_xfer_func()
96 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_xfer_func()
99 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_xfer_func()
112 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_xfer_func()
118 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_xfer_func()
124 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_xfer_func()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c76 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, in hubp2_set_vm_system_aperture_settings()
89 REG_SET_2(BLANK_OFFSET_0, 0, in hubp2_program_deadline()
99 REG_SET_2(DST_AFTER_SCALER, 0, in hubp2_program_deadline()
124 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp2_program_deadline()
146 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp2_program_deadline()
253 REG_SET_2(PREFETCH_SETTINGS, 0, in hubp2_setup_interdependent()
260 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp2_setup_interdependent()
264 REG_SET_2(FLIP_PARAMETERS_0, 0, in hubp2_setup_interdependent()
277 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp2_setup_interdependent()
292 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp2_setup_interdependent()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_vmid.c88 REG_SET_2(CNTL, 0, in dcn20_vmid_setup()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.c343 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg314_dpp_root_clock_control()
349 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg314_dpp_root_clock_control()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c88 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg21_update_dpp_dto()
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h65 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ macro
/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_ddc.c101 REG_SET_2(gpio.MASK_reg, regval, in set_config()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c64 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg2_update_dpp_dto()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.c1041 REG_SET_2(DPPCLK_DTO_PARAM[inst], 0, in dccg35_enable_dpp_clk_new()
1058 REG_SET_2(DPPCLK_DTO_PARAM[inst], 0, in dccg35_disable_dpp_clk_new()
1181 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg35_update_dpp_dto()
1681 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg35_dpp_root_clock_control()
1687 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg35_dpp_root_clock_control()
2178 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg35_update_dpp_dto_cb()

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