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Searched refs:REG_SET (Results 1 – 25 of 32) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_vmid.c78 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, in dcn20_vmid_setup()
80 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, in dcn20_vmid_setup()
83 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, in dcn20_vmid_setup()
85 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, in dcn20_vmid_setup()
92 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, in dcn20_vmid_setup()
95 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, in dcn20_vmid_setup()
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb_cm.c183 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_configure_ogam_lut()
198 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
200 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red); in dwb3_program_ogam_pwl()
208 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
210 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red); in dwb3_program_ogam_pwl()
212 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
218 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg); in dwb3_program_ogam_pwl()
220 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_green); in dwb3_program_ogam_pwl()
222 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
228 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].blue_reg); in dwb3_program_ogam_pwl()
[all …]
/linux/arch/arm/mach-imx/
H A Danatop.c16 #define REG_SET 0x4 macro
46 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c45 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc201_triplebuffer_lock()
47 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc201_triplebuffer_lock()
49 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_lock()
61 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_unlock()
63 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc201_triplebuffer_unlock()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/
H A Ddcn20_hubbub.c400 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub2_init_dchub_sys_ctx()
402 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub2_init_dchub_sys_ctx()
404 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub2_init_dchub_sys_ctx()
406 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub2_init_dchub_sys_ctx()
408 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub2_init_dchub_sys_ctx()
410 REG_SET(DCN_VM_AGP_BASE, 0, in hubbub2_init_dchub_sys_ctx()
413 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, in hubbub2_init_dchub_sys_ctx()
415 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, in hubbub2_init_dchub_sys_ctx()
622 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, in hubbub2_program_watermarks()
/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_ddc.c99 REG_SET(gpio.MASK_reg, regval, DC_GPIO_DDC1DATA_PD_EN, 1); in set_config()
118 REG_SET(gpio.MASK_reg, regval, in set_config()
127 REG_SET(gpio.MASK_reg, regval, in set_config()
163 REG_SET(gpio.MASK_reg, regval, in set_config()
/linux/drivers/thermal/
H A Dimx_thermal.c20 #define REG_SET 0x4 macro
230 regmap_write(map, soc_data->panic_alarm_ctrl + REG_SET, in imx_set_panic_temp()
250 regmap_write(map, soc_data->high_alarm_ctrl + REG_SET, in imx_set_alarm_temp()
622 regmap_write(map, data->socdata->low_alarm_ctrl + REG_SET, in imx_thermal_probe()
653 regmap_write(map, IMX6_MISC0 + REG_SET, in imx_thermal_probe()
655 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
705 regmap_write(map, data->socdata->measure_freq_ctrl + REG_SET, in imx_thermal_probe()
714 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
811 ret = regmap_write(map, socdata->sensor_ctrl + REG_SET, in imx_thermal_runtime_suspend()
837 ret = regmap_write(map, socdata->sensor_ctrl + REG_SET, in imx_thermal_runtime_resume()
/linux/drivers/gpu/drm/radeon/
H A Dr300d.h61 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
62 REG_SET(PACKET0_COUNT, (n)))
63 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
65 REG_SET(PACKET3_IT_OPCODE, (op)) | \
66 REG_SET(PACKET3_COUNT, (n)))
H A Drv515d.h201 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
202 REG_SET(PACKET0_COUNT, (n)))
203 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
205 REG_SET(PACKET3_IT_OPCODE, (op)) | \
206 REG_SET(PACKET3_COUNT, (n)))
H A Dr100d.h60 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
61 REG_SET(PACKET0_COUNT, (n)))
62 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
64 REG_SET(PACKET3_IT_OPCODE, (op)) | \
65 REG_SET(PACKET3_COUNT, (n)))
H A Drs400.c153 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); in rs400_gart_enable()
154 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); in rs400_gart_enable()
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
H A Ddcn32_mmhubbub.c83 …REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.hig… in mmhubbub32_warmup_mcif()
84 …REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_LOW, 0, MMHUBBUB_WARMUP_BASE_ADDR_LOW, start_address_shift.low_p… in mmhubbub32_warmup_mcif()
85 REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5); in mmhubbub32_warmup_mcif()
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.c101 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_dsc_pg_control()
201 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_hubp_dpp_pg_control()
278 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_hpo_pg_control()
325 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_io_clk_pg_control()
428 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_plane_otg_pg_control()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.c173 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn302_dsc_pg_control()
222 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn302_dsc_pg_control()
/linux/drivers/misc/rp1/
H A Drp1_pci.c21 #define REG_SET 0x800 macro
47 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_SET + MSIX_CFG(hwirq)); in msix_cfg_set()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c210 REG_SET(DSC_DEBUG_CONTROL, 0, in dsc_write_to_registers()
239 REG_SET(DSCC_CONFIG1, 0, in dsc_write_to_registers()
278 REG_SET(DSCC_PPS_CONFIG4, 0, in dsc_write_to_registers()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/
H A Ddcn201_hubbub.c68 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, in hubbub201_program_watermarks()
/linux/drivers/gpu/drm/mxsfb/
H A Dmxsfb_regs.h12 #define REG_SET 4 macro
H A Dlcdif_regs.h11 #define REG_SET 4 macro
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn301/
H A Ddcn301_optc.c64 REG_SET(OTG_V_TOTAL_MID, 0, in optc301_set_drr()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_afmt.c136 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); in afmt3_se_audio_setup()
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h61 #define REG_SET(reg_name, initial_val, field, val) \ macro
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c591 REG_SET(DSC_DEBUG_CONTROL, 0, in dsc_write_to_registers()
620 REG_SET(DSCC_CONFIG1, 0, in dsc_write_to_registers()
659 REG_SET(DSCC_PPS_CONFIG4, 0, in dsc_write_to_registers()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c173 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp201_cnv_setup()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvid.h103 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

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