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Searched refs:REG_SET (Results 1 – 25 of 46) sorted by relevance

12

/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c100 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
154 REG_SET( in program_gamut_remap()
269 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_cm_program_color_matrix()
303 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); in dpp1_cm_program_color_matrix()
391 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_cm_power_on_regamma_lut()
406 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); in dpp1_cm_program_regamma_lut()
407 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); in dpp1_cm_program_regamma_lut()
408 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); in dpp1_cm_program_regamma_lut()
410 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); in dpp1_cm_program_regamma_lut()
411 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); in dpp1_cm_program_regamma_lut()
[all …]
H A Ddcn10_dpp_dscl.c516 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in dpp1_dscl_set_manual_ratio_init()
519 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in dpp1_dscl_set_manual_ratio_init()
522 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0, in dpp1_dscl_set_manual_ratio_init()
525 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0, in dpp1_dscl_set_manual_ratio_init()
642 REG_SET(DSCL_CONTROL, 0, in dpp1_dscl_set_scaler_manual_scale()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.c142 REG_SET(OPTC_BYTES_PER_PIXEL, 0, in optc2_set_dsc_config()
176 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_bypass()
205 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_combine()
216 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); in optc2_set_odm_combine()
284 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_align_vblanks()
294 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_align_vblanks()
322 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_align_vblanks()
344 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_align_vblanks()
368 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_align_vblanks()
374 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_align_vblanks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_vmid.c78 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, in dcn20_vmid_setup()
80 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, in dcn20_vmid_setup()
83 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, in dcn20_vmid_setup()
85 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, in dcn20_vmid_setup()
92 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, in dcn20_vmid_setup()
95 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, in dcn20_vmid_setup()
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
H A Ddcn20_mpc.c66 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); in mpc2_update_blending()
67 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); in mpc2_update_blending()
68 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); in mpc2_update_blending()
142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
182 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
198 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
241 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
278 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
293 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); in mpc20_configure_ogam_lut()
388 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg); in mpc20_program_ogam_pwl()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp_cm.c94 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
96 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red); in dpp3_program_gammcor_lut()
102 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
104 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red); in dpp3_program_gammcor_lut()
106 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
111 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].green_reg); in dpp3_program_gammcor_lut()
113 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_green); in dpp3_program_gammcor_lut()
115 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
120 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].blue_reg); in dpp3_program_gammcor_lut()
122 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_blue); in dpp3_program_gammcor_lut()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb_cm.c183 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_configure_ogam_lut()
198 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
200 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red); in dwb3_program_ogam_pwl()
208 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
210 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red); in dwb3_program_ogam_pwl()
212 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
218 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg); in dwb3_program_ogam_pwl()
220 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_green); in dwb3_program_ogam_pwl()
222 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
228 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].blue_reg); in dwb3_program_ogam_pwl()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_ipp.c127 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, in dce_ipp_cursor_set_attributes()
130 REG_SET(CUR_SURFACE_ADDRESS, 0, in dce_ipp_cursor_set_attributes()
178 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); in dce_ipp_program_input_lut()
181 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); in dce_ipp_program_input_lut()
193 REG_SET(DC_LUT_RW_INDEX, 0, in dce_ipp_program_input_lut()
197 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
200 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
203 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
210 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); in dce_ipp_program_input_lut()
H A Ddce_transform.c120 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); in setup_scaling_configuration()
144 REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1); in setup_scaling_configuration()
154 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); in dce60_setup_scaling_configuration()
229 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1); in program_multi_taps_filter()
347 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
350 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
370 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in dce60_program_scl_ratios_inits()
373 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in dce60_program_scl_ratios_inits()
448 REG_SET(SCL_VERT_FILTER_CONTROL, 0, in dce_transform_set_scaler()
463 REG_SET(SCL_HORZ_FILTER_CONTROL, 0, in dce_transform_set_scaler()
[all …]
H A Ddce_mem_input.c506 REG_SET(GRPH_X_START, 0, in program_size_and_rotation()
509 REG_SET(GRPH_Y_START, 0, in program_size_and_rotation()
512 REG_SET(GRPH_X_END, 0, in program_size_and_rotation()
515 REG_SET(GRPH_Y_END, 0, in program_size_and_rotation()
518 REG_SET(GRPH_PITCH, 0, in program_size_and_rotation()
521 REG_SET(HW_ROTATION, 0, in program_size_and_rotation()
536 REG_SET(GRPH_X_START, 0, in dce60_program_size()
539 REG_SET(GRPH_Y_START, 0, in dce60_program_size()
542 REG_SET(GRPH_X_END, 0, in dce60_program_size()
545 REG_SET(GRPH_Y_END, 0, in dce60_program_size()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c99 REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0); in dpp2_program_degamma_lut()
101 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg); in dpp2_program_degamma_lut()
102 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg); in dpp2_program_degamma_lut()
103 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg); in dpp2_program_degamma_lut()
105 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
107 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
109 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
170 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
207 REG_SET( in program_gamut_remap()
307 REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0); in dpp2_program_input_csc()
[all …]
/linux/arch/arm/mach-imx/
H A Danatop.c16 #define REG_SET 0x4 macro
46 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c45 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc201_triplebuffer_lock()
47 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc201_triplebuffer_lock()
49 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_lock()
61 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_unlock()
63 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc201_triplebuffer_unlock()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/
H A Ddcn30_optc.c52 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc3_triplebuffer_lock()
55 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc3_triplebuffer_lock()
125 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc3_lock()
174 REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0, in optc3_set_vtotal_change_limit()
213 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc3_set_odm_bypass()
250 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc3_set_odm_combine()
270 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc3_set_odm_combine()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/
H A Ddcn20_hubbub.c400 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub2_init_dchub_sys_ctx()
402 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub2_init_dchub_sys_ctx()
404 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub2_init_dchub_sys_ctx()
406 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub2_init_dchub_sys_ctx()
408 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub2_init_dchub_sys_ctx()
410 REG_SET(DCN_VM_AGP_BASE, 0, in hubbub2_init_dchub_sys_ctx()
413 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, in hubbub2_init_dchub_sys_ctx()
415 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, in hubbub2_init_dchub_sys_ctx()
622 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, in hubbub2_program_watermarks()
/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_ddc.c99 REG_SET(gpio.MASK_reg, regval, DC_GPIO_DDC1DATA_PD_EN, 1); in set_config()
118 REG_SET(gpio.MASK_reg, regval, in set_config()
127 REG_SET(gpio.MASK_reg, regval, in set_config()
163 REG_SET(gpio.MASK_reg, regval, in set_config()
/linux/drivers/thermal/
H A Dimx_thermal.c20 #define REG_SET 0x4 macro
230 regmap_write(map, soc_data->panic_alarm_ctrl + REG_SET, in imx_set_panic_temp()
250 regmap_write(map, soc_data->high_alarm_ctrl + REG_SET, in imx_set_alarm_temp()
622 regmap_write(map, data->socdata->low_alarm_ctrl + REG_SET, in imx_thermal_probe()
653 regmap_write(map, IMX6_MISC0 + REG_SET, in imx_thermal_probe()
655 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
705 regmap_write(map, data->socdata->measure_freq_ctrl + REG_SET, in imx_thermal_probe()
714 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
811 ret = regmap_write(map, socdata->sensor_ctrl + REG_SET, in imx_thermal_runtime_suspend()
837 ret = regmap_write(map, socdata->sensor_ctrl + REG_SET, in imx_thermal_runtime_resume()
/linux/drivers/gpu/drm/radeon/
H A Dr300d.h61 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
62 REG_SET(PACKET0_COUNT, (n)))
63 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
65 REG_SET(PACKET3_IT_OPCODE, (op)) | \
66 REG_SET(PACKET3_COUNT, (n)))
H A Drv515d.h201 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
202 REG_SET(PACKET0_COUNT, (n)))
203 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
205 REG_SET(PACKET3_IT_OPCODE, (op)) | \
206 REG_SET(PACKET3_COUNT, (n)))
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_cm_common.c61 REG_SET(reg->start_slope_cntl_b, 0, //linear slope at start of curve in cm_helper_program_gamcor_xfer_func()
63 REG_SET(reg->start_slope_cntl_g, 0, in cm_helper_program_gamcor_xfer_func()
65 REG_SET(reg->start_slope_cntl_r, 0, in cm_helper_program_gamcor_xfer_func()
68 REG_SET(reg->start_end_cntl1_b, 0, in cm_helper_program_gamcor_xfer_func()
70 REG_SET(reg->start_end_cntl1_g, 0, in cm_helper_program_gamcor_xfer_func()
72 REG_SET(reg->start_end_cntl1_r, 0, in cm_helper_program_gamcor_xfer_func()
H A Ddcn30_mmhubbub.c83 …REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.hig… in mmhubbub3_warmup_mcif()
84 …REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_LOW, 0, MMHUBBUB_WARMUP_BASE_ADDR_LOW, start_address_shift.low_p… in mmhubbub3_warmup_mcif()
85 REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5); in mmhubbub3_warmup_mcif()
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
H A Ddcn32_mmhubbub.c83 …REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.hig… in mmhubbub32_warmup_mcif()
84 …REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_LOW, 0, MMHUBBUB_WARMUP_BASE_ADDR_LOW, start_address_shift.low_p… in mmhubbub32_warmup_mcif()
85 REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5); in mmhubbub32_warmup_mcif()
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.c101 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_dsc_pg_control()
201 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_hubp_dpp_pg_control()
278 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_hpo_pg_control()
325 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_io_clk_pg_control()
428 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_plane_otg_pg_control()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.c173 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn302_dsc_pg_control()
222 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn302_dsc_pg_control()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_cm_common.c103 REG_SET(reg->start_slope_cntl_b, 0, in cm_helper_program_xfer_func()
105 REG_SET(reg->start_slope_cntl_g, 0, in cm_helper_program_xfer_func()
107 REG_SET(reg->start_slope_cntl_r, 0, in cm_helper_program_xfer_func()
110 REG_SET(reg->start_end_cntl1_b, 0, in cm_helper_program_xfer_func()
116 REG_SET(reg->start_end_cntl1_g, 0, in cm_helper_program_xfer_func()
122 REG_SET(reg->start_end_cntl1_r, 0, in cm_helper_program_xfer_func()

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