Searched refs:REG_PTR (Results 1 – 3 of 3) sorted by relevance
| /linux/arch/riscv/kernel/ |
| H A D | traps_misaligned.c | 137 #define REG_PTR(insn, pos, regs) \ macro
140 #define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
141 #define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
142 #define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
143 #define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
144 #define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
145 #define GET_SP(regs) (*REG_PTR(2, 0, regs))
146 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
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| /linux/arch/riscv/kvm/ |
| H A D | vcpu_insn.c | 123 #define REG_PTR(insn, pos, regs) \ macro
128 #define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
129 #define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
130 #define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
131 #define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
132 #define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
133 #define GET_SP(regs) (*REG_PTR(2, 0, regs))
134 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
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| /linux/arch/alpha/kernel/ |
| H A D | pc873xx.h | 11 #define REG_PTR 0x02 macro
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