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Searched refs:REG_FIELD (Results 1 – 25 of 43) sorted by relevance

12

/linux/drivers/power/supply/
H A Dbd99954-charger.h482 [F_PREV_CHGSTM_STATE] = REG_FIELD(CHGSTM_STATUS, 8, 14),
483 [F_CHGSTM_STATE] = REG_FIELD(CHGSTM_STATUS, 0, 6),
484 [F_VBAT_VSYS_STATUS] = REG_FIELD(VBAT_VSYS_STATUS, 0, 15),
485 [F_VBUS_VCC_STATUS] = REG_FIELD(VBUS_VCC_STATUS, 0, 12),
486 [F_BATTEMP] = REG_FIELD(CHGOP_STATUS, 8, 10),
487 [F_VRECHG_DET] = REG_FIELD(CHGOP_STATUS, 6, 6),
488 [F_RBOOST_UV] = REG_FIELD(CHGOP_STATUS, 1, 1),
489 [F_RBOOSTS] = REG_FIELD(CHGOP_STATUS, 0, 0),
490 [F_THERMWDT_VAL] = REG_FIELD(WDT_STATUS, 8, 15),
491 [F_CHGWDT_VAL] = REG_FIELD(WDT_STATUS, 0, 7),
[all …]
H A Drt9471.c169 [F_WDT] = REG_FIELD(RT9471_REG_TOP, 0, 1),
170 [F_WDT_RST] = REG_FIELD(RT9471_REG_TOP, 2, 2),
171 [F_CHG_EN] = REG_FIELD(RT9471_REG_FUNC, 0, 0),
172 [F_HZ] = REG_FIELD(RT9471_REG_FUNC, 5, 5),
173 [F_BATFET_DIS] = REG_FIELD(RT9471_REG_FUNC, 7, 7),
174 [F_AICR] = REG_FIELD(RT9471_REG_IBUS, 0, 5),
175 [F_AICC_EN] = REG_FIELD(RT9471_REG_IBUS, 7, 7),
176 [F_MIVR] = REG_FIELD(RT9471_REG_VBUS, 0, 3),
177 [F_IPRE_CHG] = REG_FIELD(RT9471_REG_PRECHG, 0, 3),
178 [F_VPRE_CHG] = REG_FIELD(RT9471_REG_PRECHG, 4, 6),
[all …]
H A Dmax8971_charger.c87 [THM_DTLS] = REG_FIELD(MAX8971_REG_DETAILS1, 0, 2),
88 [BAT_DTLS] = REG_FIELD(MAX8971_REG_DETAILS2, 4, 5),
89 [CHG_DTLS] = REG_FIELD(MAX8971_REG_DETAILS2, 0, 3),
90 [CHG_CC] = REG_FIELD(MAX8971_REG_FCHGCRNT, 0, 4),
91 [FCHG_T] = REG_FIELD(MAX8971_REG_FCHGCRNT, 5, 7),
92 [DCI_LMT] = REG_FIELD(MAX8971_REG_DCCRNT, 0, 5),
93 [TOPOFF_T] = REG_FIELD(MAX8971_REG_TOPOFF, 5, 7),
94 [TOPOFF_S] = REG_FIELD(MAX8971_REG_TOPOFF, 2, 3),
95 [CPROT] = REG_FIELD(MAX8971_REG_PROTCMD, 2, 3),
/linux/drivers/usb/isp1760/
H A Disp1760-core.c184 [HCS_PPC] = REG_FIELD(ISP176x_HC_HCSPARAMS, 4, 4),
185 [HCS_N_PORTS] = REG_FIELD(ISP176x_HC_HCSPARAMS, 0, 3),
186 [HCC_ISOC_CACHE] = REG_FIELD(ISP176x_HC_HCCPARAMS, 7, 7),
187 [HCC_ISOC_THRES] = REG_FIELD(ISP176x_HC_HCCPARAMS, 4, 6),
188 [CMD_LRESET] = REG_FIELD(ISP176x_HC_USBCMD, 7, 7),
189 [CMD_RESET] = REG_FIELD(ISP176x_HC_USBCMD, 1, 1),
190 [CMD_RUN] = REG_FIELD(ISP176x_HC_USBCMD, 0, 0),
191 [STS_PCD] = REG_FIELD(ISP176x_HC_USBSTS, 2, 2),
192 [HC_FRINDEX] = REG_FIELD(ISP176x_HC_FRINDEX, 0, 13),
193 [FLAG_CF] = REG_FIELD(ISP176x_HC_CONFIGFLAG, 0, 0),
[all …]
/linux/drivers/thermal/qcom/
H A Dtsens.h91 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \
92 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \
93 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \
94 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \
95 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \
96 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \
97 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \
98 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \
99 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \
100 [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \
[all …]
H A Dtsens-8960.c207 [TSENS_EN] = REG_FIELD(CNTL_ADDR, 0, 0),
208 [TSENS_SW_RST] = REG_FIELD(CNTL_ADDR, 1, 1),
210 [SENSOR_EN] = REG_FIELD(CNTL_ADDR, 3, 7),
217 [LOW_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 0, 7),
218 [UP_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 8, 15),
224 [CRIT_THRESH_1] = REG_FIELD(THRESHOLD_ADDR, 16, 23),
225 [CRIT_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 24, 31),
229 [LOW_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 9, 9),
230 [UP_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 10, 10),
235 [LAST_TEMP_0] = REG_FIELD(S0_STATUS_OFF, 0, 7),
[all …]
H A Dtsens-v1.c96 [VER_MAJOR] = REG_FIELD(SROT_HW_VER_OFF, 28, 31),
97 [VER_MINOR] = REG_FIELD(SROT_HW_VER_OFF, 16, 27),
98 [VER_STEP] = REG_FIELD(SROT_HW_VER_OFF, 0, 15),
100 [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0),
101 [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1),
102 [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 13),
106 [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
115 [LOW_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 0, 0),
116 [LOW_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 1, 1),
117 [LOW_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 2, 2),
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_reg.c283 [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0),
284 [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5),
285 [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14),
286 [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18),
287 [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31),
288 [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31),
289 [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31),
290 [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31),
291 [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31),
292 [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19),
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_enc.c344 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
348 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
349 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
350 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
351 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
352 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
353 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
354 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
355 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
356 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
[all …]
/linux/drivers/net/ethernet/mscc/
H A Dvsc7514_regs.c13 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11),
14 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10),
15 [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27),
16 [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26),
17 [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25),
18 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
19 [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23),
20 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
21 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
22 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
[all …]
/linux/drivers/regulator/
H A Dda9062-regulator.c378 .sleep = REG_FIELD(DA9062AA_VBUCK1_A,
382 .suspend_sleep = REG_FIELD(DA9062AA_VBUCK1_B,
387 .mode = REG_FIELD(DA9062AA_BUCK1_CFG,
391 .suspend = REG_FIELD(DA9062AA_BUCK1_CONT,
415 .sleep = REG_FIELD(DA9062AA_VBUCK3_A,
419 .suspend_sleep = REG_FIELD(DA9062AA_VBUCK3_B,
424 .mode = REG_FIELD(DA9062AA_BUCK3_CFG,
428 .suspend = REG_FIELD(DA9062AA_BUCK3_CONT,
452 .sleep = REG_FIELD(DA9062AA_VBUCK4_A,
456 .suspend_sleep = REG_FIELD(DA9062AA_VBUCK4_B,
[all …]
/linux/drivers/phy/ti/
H A Dphy-am654-serdes.c198 [CMU_PLL_CTRL] = REG_FIELD(CMU_R004, 8, 15),
199 [AHB_PMA_CM_VCO_VBIAS_VREG] = REG_FIELD(CMU_R060, 8, 15),
200 [CMU_MASTER_CDN] = REG_FIELD(CMU_R07C, 24, 31),
201 [AHB_PMA_CM_VCO_BIAS_VREG] = REG_FIELD(CMU_R088, 24, 31),
202 [AHB_PMA_CM_SR] = REG_FIELD(CMU_R0D0, 24, 31),
203 [AHB_SSC_GEN_Z_O_20_13] = REG_FIELD(CMU_R0E8, 8, 15),
204 [LANE_PLL_CTRL_RXEQ_RXIDLE] = REG_FIELD(LANE_R048, 8, 15),
205 [AHB_PMA_LN_AGC_THSEL_VREGH] = REG_FIELD(LANE_R058, 16, 23),
206 [AHB_PMA_LN_GEN3_AGC_SD_THSEL] = REG_FIELD(LANE_R06c, 0, 7),
207 [AHB_PMA_LN_RX_SELR_GEN3] = REG_FIELD(LANE_R070, 16, 23),
[all …]
H A Dphy-gmii-sel.c175 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 0, 1),
176 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 4, 4),
177 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 6, 6),
180 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 2, 3),
181 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 5, 5),
182 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 7, 7),
197 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 0, 1),
200 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 4, 5),
220 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2),
221 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x0, 4, 4),
[all …]
H A Dphy-j721e-wiz.c87 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
88 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
89 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30);
91 REG_FIELD(WIZ_SERDES_RST, 29, 29);
93 REG_FIELD(WIZ_SERDES_RST, 22, 23);
95 REG_FIELD(WIZ_SERDES_RST, 28, 28);
97 REG_FIELD(WIZ_SERDES_RST, 28, 29);
99 REG_FIELD(WIZ_SERDES_RST, 24, 25);
101 REG_FIELD(WIZ_SERDES_RST, 24, 24);
103 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
[all …]
/linux/drivers/leds/rgb/
H A Dleds-mt6370-rgb.c159 [F_RGB_EN] = REG_FIELD(MT6370_REG_RGB_EN, 4, 7),
160 [F_CHGIND_EN] = REG_FIELD(MT6370_REG_RGB_CHRIND_DIM, 7, 7),
161 [F_LED1_CURR] = REG_FIELD(MT6370_REG_RGB1_ISNK, 0, 2),
162 [F_LED2_CURR] = REG_FIELD(MT6370_REG_RGB2_ISNK, 0, 2),
163 [F_LED3_CURR] = REG_FIELD(MT6370_REG_RGB3_ISNK, 0, 2),
164 [F_LED4_CURR] = REG_FIELD(MT6370_REG_RGB_CHRIND_CTRL, 0, 1),
165 [F_LED1_MODE] = REG_FIELD(MT6370_REG_RGB1_DIM, 5, 6),
166 [F_LED2_MODE] = REG_FIELD(MT6370_REG_RGB2_DIM, 5, 6),
167 [F_LED3_MODE] = REG_FIELD(MT6370_REG_RGB3_DIM, 5, 6),
168 [F_LED4_MODE] = REG_FIELD(MT6370_REG_RGB_CHRIND_DIM, 5, 6),
[all …]
/linux/sound/soc/jz4740/
H A Djz4740-i2s.c363 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 12, 15),
364 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11),
365 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
366 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
372 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27),
373 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
374 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
375 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
380 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27),
381 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
[all …]
/linux/drivers/net/ethernet/ti/
H A Dcpsw_ale.c1330 [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7),
1331 [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 15),
1336 [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7),
1337 [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 10),
1339 [ALE_ENTRIES] = REG_FIELD(ALE_STATUS, 0, 7),
1340 [ALE_POLICERS] = REG_FIELD(ALE_STATUS, 8, 15),
1342 [POL_PORT_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 31, 31),
1343 [POL_TRUNK_ID] = REG_FIELD(ALE_POLICER_PORT_OUI, 30, 30),
1344 [POL_PORT_NUM] = REG_FIELD(ALE_POLICER_PORT_OUI, 25, 25),
1345 [POL_PRI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 19, 19),
[all …]
/linux/drivers/rtc/
H A Drtc-ti-k3.c83 [K3RTC_KICK0] = REG_FIELD(REG_K3RTC_KICK0, 0, 31),
84 [K3RTC_KICK1] = REG_FIELD(REG_K3RTC_KICK1, 0, 31),
85 [K3RTC_S_CNT_LSW] = REG_FIELD(REG_K3RTC_S_CNT_LSW, 0, 31),
86 [K3RTC_S_CNT_MSW] = REG_FIELD(REG_K3RTC_S_CNT_MSW, 0, 15),
87 [K3RTC_O32K_OSC_DEP_EN] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 21, 21),
88 [K3RTC_UNLOCK] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 23, 23),
89 [K3RTC_CNT_FMODE] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 24, 25),
90 [K3RTC_PEND] = REG_FIELD(REG_K3RTC_SYNCPEND, 0, 1),
91 [K3RTC_RELOAD_FROM_BBD] = REG_FIELD(REG_K3RTC_SYNCPEND, 31, 31),
92 [K3RTC_COMP] = REG_FIELD(REG_K3RTC_COMP, 0, 31),
[all …]
/linux/drivers/reset/sti/
H A Dreset-syscfg.h30 .reset = REG_FIELD(_rr, _rb, _rb), \
31 .ack = REG_FIELD(_ar, _ab, _ab), }
35 .reset = REG_FIELD(_rr, _rb, _rb), }
/linux/sound/soc/sunxi/
H A Dsun4i-i2s.c1367 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1368 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
1369 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
1386 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1387 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
1388 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
1410 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1411 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
1412 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
1429 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
[all …]
/linux/sound/soc/meson/
H A Dg12a-toacodec.c267 .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, 14, 15),
268 .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, 8, 9),
269 .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 5),
274 .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, 18, 19),
275 .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, 12, 14),
276 .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 6),
/linux/drivers/clk/mstar/
H A Dclk-msc313-mpll.c22 static const struct reg_field config1_loop_div_first = REG_FIELD(REG_CONFIG1, 8, 9);
23 static const struct reg_field config1_input_div_first = REG_FIELD(REG_CONFIG1, 4, 5);
24 static const struct reg_field config2_output_div_first = REG_FIELD(REG_CONFIG2, 12, 13);
25 static const struct reg_field config2_loop_div_second = REG_FIELD(REG_CONFIG2, 0, 7);
/linux/drivers/iio/adc/
H A Drtq6056.c101 [F_OPMODE] = REG_FIELD(RTQ6056_REG_CONFIG, 0, 2),
102 [F_VSHUNTCT] = REG_FIELD(RTQ6056_REG_CONFIG, 3, 5),
103 [F_VBUSCT] = REG_FIELD(RTQ6056_REG_CONFIG, 6, 8),
104 [F_AVG] = REG_FIELD(RTQ6056_REG_CONFIG, 9, 11),
105 [F_RESET] = REG_FIELD(RTQ6056_REG_CONFIG, 15, 15),
109 [F_OPMODE] = REG_FIELD(RTQ6056_REG_CONFIG, 0, 2),
110 [F_RTQ6059_SADC] = REG_FIELD(RTQ6056_REG_CONFIG, 3, 6),
111 [F_RTQ6059_BADC] = REG_FIELD(RTQ6056_REG_CONFIG, 7, 10),
112 [F_RTQ6059_PGA] = REG_FIELD(RTQ6056_REG_CONFIG, 11, 12),
113 [F_RESET] = REG_FIELD(RTQ6056_REG_CONFIG, 15, 15),
/linux/drivers/pwm/
H A Dpwm-sti.c99 [PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3),
100 [PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14),
101 [CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8),
102 [PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9),
103 [PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10),
104 [PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4),
105 [PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4),
/linux/drivers/iio/light/
H A Dapds9160.c508 REG_FIELD(APDS9160_REG_CTRL, 1, 1);
511 REG_FIELD(APDS9160_REG_CTRL, 0, 0);
514 REG_FIELD(APDS9160_REG_INT_CFG, 0, 0);
517 REG_FIELD(APDS9160_REG_INT_CFG, 2, 2);
520 REG_FIELD(APDS9160_REG_PS_DATA_MSB, 3, 3);
523 REG_FIELD(APDS9160_REG_LS_MEAS_RATE, 0, 2);
526 REG_FIELD(APDS9160_REG_LS_GAIN, 0, 2);
529 REG_FIELD(APDS9160_REG_PS_MEAS_RATE, 0, 2);
532 REG_FIELD(APDS9160_REG_LS_MEAS_RATE, 4, 6);
535 REG_FIELD(APDS9160_REG_PS_LED, 0, 2);
[all …]

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