Searched refs:REG_EP2RC_SW_INT_EAP_MASK_CLR (Results 1 – 2 of 2) sorted by relevance
92 iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_CLR); in t7xx_mhccif_mask_clr()
46 #define REG_EP2RC_SW_INT_EAP_MASK_CLR 0x40 macro