Searched refs:REG_CLR (Results 1 – 7 of 7) sorted by relevance
| /linux/arch/arm/mach-imx/ |
| H A D | anatop.c | 17 #define REG_CLR 0x8 macro 46 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5() 52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive() 58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown() 64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
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| /linux/drivers/thermal/ |
| H A D | imx_thermal.c | 21 #define REG_CLR 0x8 macro 228 regmap_write(map, soc_data->panic_alarm_ctrl + REG_CLR, in imx_set_panic_temp() 248 regmap_write(map, soc_data->high_alarm_ctrl + REG_CLR, in imx_set_alarm_temp() 615 regmap_write(map, IMX6_MISC1 + REG_CLR, in imx_thermal_probe() 646 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe() 648 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe() 650 regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR, in imx_thermal_probe() 702 regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR, in imx_thermal_probe() 712 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe() 806 ret = regmap_write(map, socdata->sensor_ctrl + REG_CLR, in imx_thermal_runtime_suspend() [all …]
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| /linux/drivers/gpu/drm/mxsfb/ |
| H A D | mxsfb_drv.c | 173 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_handler() 185 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable() 186 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
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| H A D | mxsfb_regs.h | 13 #define REG_CLR 8 macro
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| H A D | lcdif_regs.h | 12 #define REG_CLR 8 macro
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| H A D | lcdif_kms.c | 398 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR); in lcdif_reset_block()
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| /linux/drivers/misc/rp1/ |
| H A D | rp1_pci.c | 22 #define REG_CLR 0xc00 macro 52 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq)); in msix_cfg_clr()
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