Searched refs:RADEON_MCLK_CNTL (Results 1 – 2 of 2) sorted by relevance
88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()605 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()620 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()635 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()812 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()817 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()882 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()885 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
1175 #define RADEON_MCLK_CNTL 0x0012 /* PLL */ macro