Searched refs:R9A09G057_CA55_0_CORE_CLK0 (Results 1 – 3 of 3) sorted by relevance
12 #define R9A09G057_CA55_0_CORE_CLK0 1 macro
85 DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55,
66 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;