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Searched refs:R8 (Results 1 – 25 of 91) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td29 // A SwiftError is passed in R8.
30 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
55 // A SwiftError is returned in R8.
56 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
175 // A SwiftError is passed in R8.
176 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
193 // A SwiftError is returned in R8.
194 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
220 // A SwiftError is passed in R8.
[all …]
H A DThumb1InstrInfo.cpp32 .addReg(ARM::R8) in getNop()
33 .addReg(ARM::R8) in getNop()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp40 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
45 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
50 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
56 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td63 def R8 : MSP430RegWithSubregs<8, "r8", [R8B]>, DwarfRegNum<[8]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/freebsd/sys/amd64/amd64/
H A Dbpf_jit_machdep.c211 MOVrq2(RDI, R8); in bpf_jit_compile()
255 MOVrq3(R8, RCX); in bpf_jit_compile()
274 MOVrq3(R8, RCX); in bpf_jit_compile()
289 MOVrq3(R8, RCX); in bpf_jit_compile()
322 MOVrq3(R8, RCX); in bpf_jit_compile()
346 MOVrq3(R8, RCX); in bpf_jit_compile()
365 MOVrq3(R8, RCX); in bpf_jit_compile()
383 MOVrq3(R8, RCX); in bpf_jit_compile()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td33 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
H A DXCoreRegisterInfo.cpp213 XCore::R8, XCore::R9, XCore::R10, in getCalleeSavedRegs()
218 XCore::R8, XCore::R9, in getCalleeSavedRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td34 def RV : LanaiReg< 8, "rv", [R8]>, DwarfRegAlias<R8>;
51 R8, RV, // return value
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_ldlib_asm.S59 #define exp R8
158 #define exp R8
257 #define mantbl_ R8
262 #define c8001 R8
H A Dfastmath2_dlib_asm.S65 #define exp R8
166 #define exp R8
268 #define exp R8
H A Dfastmath_dlib_asm.S67 #define exp R8
202 #define exp R8
330 #define exp R8
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp73 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
98 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
150 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFCallingConv.td48 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
49 def CSR_PreserveAll : CalleeSavedRegs<(add R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10)>;
H A DBPFFrameLowering.cpp36 SavedRegs.reset(BPF::R8); in determineCalleeSaves()
/freebsd/contrib/arm-optimized-routines/math/aarch64/experimental/
H A Derfc_1u8.c35 #define R8 -0x1.6c16c16c16c17p-3 macro
110 double p9 = fma (Q8 * r, p8, p7) * R8; in erfc()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.cpp42 return TFI->hasFP(MF) ? CSKY::R8 : CSKY::R14; in getFrameRegister()
56 markSuperRegs(Reserved, CSKY::R8); // fp in getReservedRegs()
60 markSuperRegs(Reserved, CSKY::R8 + i); // R8 - R13 in getReservedRegs()
H A DCSKYCallingConv.td13 def CSR_I32 : CalleeSavedRegs<(add R8, R15, (sequence "R%u", 4, 7),
21 def CSR_GPR_ISR : CalleeSavedRegs<(add R8, R15,
/freebsd/lib/msun/ld128/
H A Ds_asinpil.c64 R8 = 5.47609957562826794808966842094709768e-04L, in __r() local
79 r = R5 + (R6 + (R7 + (R8 + (R9 + R10 * xs) * xs) *xs) * xs) * xs; in __r()
H A Ds_atanpil.c71 R8 = 5.47609957562826794808966842094709768e-04L, in __r() local
86 r = R5 + (R6 + (R7 + (R8 + (R9 + R10 * xs) * xs) *xs) * xs) * xs; in __r()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td44 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
91 def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>;
121 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1)>;
125 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDebugSupport.h224 UINT64 R8; member
295 UINT64 R8; member
499 UINT32 R8; member
764 UINT64 R8; member
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15];
109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
420 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
560 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
659 [RCX , RDX , R8 , R9 ]>>,
672 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
675 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
697 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
718 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
[all …]
H A DX86CallingConv.cpp86 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9}; in CC_X86_64_VectorCallGetGPRs()
361 X86::RCX, X86::R8, X86::R9}; in CC_X86_64_I128()
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dwm8741.txt16 DIFF in register R8 (MODE_CONTROL_2). If absent, the default is 0, shall be:
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h61 case Lanai::R8: in getLanaiRegisterNumbering()

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