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Searched refs:R31 (Results 1 – 25 of 38) sorted by relevance

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/freebsd/crypto/openssl/crypto/sha/asm/
H A Dkeccak1600-avx512vl.pl56 my ($R20,$R01,$R31,$R21,$R41,$R11) = map("%ymm$_",(16..21));
99 vprolvq $R31,$A31,$A31
212 vmovdqa64 2*32(%r8),$R31
298 vmovdqa64 2*32(%r8),$R31
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPseudo.td81 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
182 Defs = [PC, R31, R6, R7, P0] in
198 // 4) All the other registers (R29, R30, R31, PC) get modified by the call
204 let hasSideEffects = 1, isCall = 1, Defs = [R0, R14, R15, R28, R29, R30, R31, PC] in
375 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
381 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
390 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
396 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
405 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
H A DHexagonRegisterInfo.cpp52 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, in HexagonRegisterInfo()
147 Reserved.set(Hexagon::R31); in getReservedRegs()
H A DHexagonRegisterInfo.td133 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
152 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>;
535 R10, R11, R29, R30, R31)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td67 def R31 : AVRReg<31, "r31", [], ["zh"]>, DwarfRegNum<[31]>;
79 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
118 R30, R31, R26, R27,
133 R30, R31, R26, R27,
H A DAVRInstrFormats.td494 // d = R16 ~ R31
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h111 case Lanai::R31: in getLanaiRegisterNumbering()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchBaseInfo.cpp191 MCRegister getBPReg() { return LoongArch::R31; } in getBPReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp279 if (Hexagon::R31 == DstReg) in getDuplexCandidateGroup()
296 if ((Hexagon::P0 == SrcReg) && (Hexagon::R31 == DstReg)) { in getDuplexCandidateGroup()
629 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
632 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
H A DHexagonMCChecker.cpp110 if (Hexagon::R31 != R && MCID.isCall()) in init()
H A DHexagonMCTargetDesc.cpp372 InitHexagonMCRegisterInfo(X, Hexagon::R31, /*DwarfFlavour=*/0, in createHexagonMCRegisterInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td83 def R31 : CSKYReg<31, "r31", ["tls"]>, DwarfRegNum<[31]>;
156 (sequence "R%u", 29, 30), R14, R31)> {
H A DCSKYRegisterInfo.cpp76 markSuperRegs(Reserved, CSKY::R31); // tp in getReservedRegs()
H A DCSKYISelLowering.cpp470 assert(RegLo < CSKY::R31 && "Invalid register pair"); in LowerReturn()
599 assert(RegLo < CSKY::R31 && "Invalid register pair"); in LowerCall()
895 .Case("{tls}", CSKY::R31) in getRegForInlineAsmConstraint()
1303 SDValue TPReg = DAG.getRegister(CSKY::R31, MVT::i32); in getStaticTLSAddr()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp120 {PPC::R31, -4}, \ in getCalleeSavedSpillSlots()
391 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; in replaceFPWithRealFP()
654 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31; in emitPrologue()
1576 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31; in emitEpilogue()
2030 SavedRegs.reset(isPPC64 ? PPC::X31 : PPC::R31); in determineCalleeSaves()
2035 if (!needsFP(MF) && !SavedRegs.test(isPPC64 ? PPC::X31 : PPC::R31) && in determineCalleeSaves()
2040 SavedRegs.set(isPPC64 ? PPC::X31 : PPC::R31); in determineCalleeSaves()
2095 unsigned MinGPR = PPC::R31; in processFunctionBeforeFrameFinalized()
2759 MCPhysReg LowestGPR = PPC::R31; in updateCalleeSaves()
H A DPPCCallingConv.td302 R28, R29, R30, R31, CR2, CR3, CR4
324 R29, R30, R31, F14, F15, F16, F17, F18,
H A DPPCRegisterInfo.cpp402 markSuperRegs(Reserved, PPC::R31); in getReservedRegs()
836 .addReg(PPC::R31) in prepareDynamicAlloca()
1930 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; in getFrameRegister()
/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDebugSupport.h318 UINT64 R31; member
787 UINT64 R31; member
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp166 Lanai::R30, Lanai::R31};
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h319 ENTRY(R31)
353 ENTRY(R31)
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td91 def R31 : LoongArchReg<31, "r31", ["s8"]>, DwarfRegNum<[31]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp67 AVR::R28, AVR::R29, AVR::R30, AVR::R31,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td93 // and regression. We don't know if we should assign cost to R16-R31 w/o
319 def R31 : X86Reg<"r31", 31, [R31D]>, DwarfRegNum<[145, -2, -2]>;
593 R18, R19, R22, R23, R24, R25, R26, R27, R30, R31, RBX,
H A DX86InstrPredicates.td26 // R16-R31 and make them allocatable only when the feature EGPR is available.
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp70 CSKY::R28, CSKY::R29, CSKY::R30, CSKY::R31};

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