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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td50 def R30 : Core<30, "%r30">, DwarfRegNum<[30]>;
64 (add (sequence "R%u", 0, 25), GP, FP, SP, ILINK, R30, BLINK, (sequence "R%u", 32, 63))> {
65 let AltOrders=[(add (sequence "R%u", 0, 25), GP, FP, SP, ILINK, R30, BLINK)];
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPseudo.td81 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
198 // 4) All the other registers (R29, R30, R31, PC) get modified by the call
204 let hasSideEffects = 1, isCall = 1, Defs = [R0, R14, R15, R28, R29, R30, R31, PC] in
270 let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
375 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
381 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
390 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
396 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
H A DHexagonRegisterInfo.cpp146 Reserved.set(Hexagon::R30); in getReservedRegs()
407 return Hexagon::R30; in getFrameRegister()
H A DHexagonDepMappings.td85 …_map_to_raw_fAlias : InstAlias<"if (!$Pv4) dealloc_return", (L4_return_f D15, PredRegs:$Pv4, R30)>;
86 …lias : InstAlias<"if (!$Pv4.new) dealloc_return:nt", (L4_return_fnew_pnt D15, PredRegs:$Pv4, R30)>;
87 …tAlias : InstAlias<"if (!$Pv4.new) dealloc_return:t", (L4_return_fnew_pt D15, PredRegs:$Pv4, R30)>;
88 …n_map_to_raw_tAlias : InstAlias<"if ($Pv4) dealloc_return", (L4_return_t D15, PredRegs:$Pv4, R30)>;
89 …Alias : InstAlias<"if ($Pv4.new) dealloc_return:nt", (L4_return_tnew_pnt D15, PredRegs:$Pv4, R30)>;
90 …ptAlias : InstAlias<"if ($Pv4.new) dealloc_return:t", (L4_return_tnew_pt D15, PredRegs:$Pv4, R30)>;
94 def L6_deallocframe_map_to_rawAlias : InstAlias<"deallocframe", (L2_deallocframe D15, R30)>;
95 def L6_return_map_to_rawAlias : InstAlias<"dealloc_return", (L4_return D15, R30)>;
H A DHexagonRegisterInfo.td132 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
152 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>;
535 R10, R11, R29, R30, R31)>;
H A DHexagonFrameLowering.cpp791 .addReg(Hexagon::R30); in insertEpilogueInBlock()
841 .addReg(Hexagon::R30); in insertEpilogueInBlock()
847 .addReg(Hexagon::R30); in insertEpilogueInBlock()
868 .addReg(Hexagon::R30); in insertEpilogueInBlock()
H A DHexagonISelLowering.cpp375 .Case("r30", Hexagon::R30) in getRegisterByName()
394 .Case("fp", Hexagon::R30) in getRegisterByName()
3350 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT), in LowerEH_RETURN()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp289 MI.getOperand(1).getReg() == Hexagon::R30) { in remapInstruction()
297 MI.getOperand(1).getReg() == Hexagon::R30) { in remapInstruction()
305 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
313 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
321 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
329 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
337 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
345 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
649 Hexagon::R30, Hexagon::R31}; in DecodeIntRegsRegisterClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td66 def R30 : AVRReg<30, "r30", [], ["zl"]>, DwarfRegNum<[30]>;
79 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
118 R30, R31, R26, R27,
133 R30, R31, R26, R27,
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h109 case Lanai::R30: in getLanaiRegisterNumbering()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp121 {PPC::R30, -8}, \ in getCalleeSavedSpillSlots()
831 .addReg(PPC::R30) in emitPrologue()
1032 .addReg(PPC::R30, RegState::Kill) // Save PIC base pointer. in emitPrologue()
1064 .addReg(PPC::R30) in emitPrologue()
1089 .addReg(PPC::R30) in emitPrologue()
1140 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true); in emitPrologue()
1822 BuildMI(MBB, MBBI, dl, LoadInst, PPC::R30) in emitEpilogue()
2038 (RegInfo->getBaseRegister(MF) == (isPPC64 ? PPC::X30 : PPC::R30)) && in determineCalleeSaves()
2044 SavedRegs.reset(PPC::R30); in determineCalleeSaves()
2197 MinGPR = std::min<unsigned>(MinGPR, PPC::R30); in processFunctionBeforeFrameFinalized()
H A DPPCCallingConv.td302 R28, R29, R30, R31, CR2, CR3, CR4
324 R29, R30, R31, F14, F15, F16, F17, F18,
H A DPPCRegisterInfo.cpp409 markSuperRegs(Reserved, PPC::R30); in getReservedRegs()
413 markSuperRegs(Reserved, PPC::R30); in getReservedRegs()
1946 return PPC::R30; in getBaseRegister()
/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDebugSupport.h317 UINT64 R30; member
786 UINT64 R30; member
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp166 Lanai::R30, Lanai::R31};
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h318 ENTRY(R30) \
352 ENTRY(R30) \
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.cpp75 markSuperRegs(Reserved, CSKY::R30); in getReservedRegs()
H A DCSKYRegisterInfo.td82 def R30 : CSKYReg<30, "r30", ["svbr"]>, DwarfRegNum<[30]>;
H A DCSKYInstrInfo16Instr.td245 let Uses = [R30];
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp129 ARC::SP, ARC::ILINK, ARC::R30, ARC::BLINK};
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td90 def R30 : LoongArchReg<30, "r30", ["s7"]>, DwarfRegNum<[30]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp67 AVR::R28, AVR::R29, AVR::R30, AVR::R31,
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp70 CSKY::R28, CSKY::R29, CSKY::R30, CSKY::R31};
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp384 nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0); in createHexagonMCAsmInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td318 def R30 : X86Reg<"r30", 30, [R30D]>, DwarfRegNum<[144, -2, -2]>;
593 R18, R19, R22, R23, R24, R25, R26, R27, R30, R31, RBX,

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