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Searched refs:R28 (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRCallingConv.td40 def CSR_Normal : CalleeSavedRegs<(add R29, R28, (sequence "R%u", 17, 2))>;
41 def CSR_NormalTiny : CalleeSavedRegs<(add R29, R28, R19, R18)>;
H A DAVRRegisterInfo.cpp87 Reserved.set(AVR::R28); in getReservedRegs()
176 BuildMI(MBB, MI, dl, TII.get(AVR::MOVRdRr), DstLoReg).addReg(AVR::R28); in eliminateFrameIndex()
285 return AVR::R28; in getFrameRegister()
H A DAVRRegisterInfo.td64 def R28 : AVRReg<28, "r28", [], ["yl"]>, DwarfRegNum<[28]>;
80 def R29R28 : AVRReg<28, "r29:r28", [R28, R29], ["Y"]>, DwarfRegNum<[28]>;
120 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
135 R28, R29, R17, R16)>;
H A DAVRFrameLowering.cpp425 SavedRegs.set(AVR::R28); in determineCalleeSaves()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPseudo.td194 // 2) R14, R15 and R28 are reserved for PLT handling and therefore are
204 let hasSideEffects = 1, isCall = 1, Defs = [R0, R14, R15, R28, R29, R30, R31, PC] in
256 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
381 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
396 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
417 let Defs = [R14, R15, R28] in
420 let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
423 let Defs = [R14, R15, R28, P0] in
426 let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h105 case Lanai::R28: in getLanaiRegisterNumbering()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td80 def R28 : CSKYReg<28, "r28", ["rgb"]>, DwarfRegNum<[28]>;
155 (sequence "R%u", 16, 17), (sequence "R%u", 26, 27), R28,
H A DCSKYCallingConv.td14 (sequence "R%u", 9, 11), (sequence "R%u", 16, 17), R28)>;
H A DCSKYInstrInfo.cpp590 BuildMI(FirstMBB, MBBI, DL, get(CSKY::LRW32), CSKY::R28) in getGlobalBaseReg()
596 .addReg(CSKY::R28); in getGlobalBaseReg()
H A DCSKYRegisterInfo.cpp73 markSuperRegs(Reserved, CSKY::R28); // gp in getReservedRegs()
/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDebugSupport.h315 UINT64 R28; member
784 UINT64 R28; member
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYInstPrinter.cpp257 printRegName(O, CSKY::R28); in printRegisterList()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp165 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h316 ENTRY(R28) \
350 ENTRY(R28) \
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td302 R28, R29, R30, R31, CR2, CR3, CR4
323 R21, R22, R23, R24, R25, R26, R27, R28,
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td88 def R28 : LoongArchReg<28, "r28", ["s5"]>, DwarfRegNum<[28]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp67 AVR::R28, AVR::R29, AVR::R30, AVR::R31,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td316 def R28 : X86Reg<"r28", 28, [R28D]>, DwarfRegNum<[142, -2, -2]>;
544 // Allocate R12, R13, R20, R21, R28 and R29 last, as these require an extra byte
594 R14, R15, R12, R13, R20, R21, R28, R29, RBP, RSP, RIP)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp70 CSKY::R28, CSKY::R29, CSKY::R30, CSKY::R31};
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am68-phyboard-izar.dts173 J721S2_IOPAD(0x074, PIN_INPUT, 8) /* (R28) MCAN2_TX.SPI6_D1 */
H A Dk3-am68-sk-base-board.dts311 J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */
H A Dk3-j721e-common-proc-board.dts236 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp349 from != CSKY::R28) in isLegalRegList()
588 else if (ListFrom == ListTo && ListFrom == CSKY::R28) in getListValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h1343 case X86::R28: in needSIB()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp648 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, in DecodeIntRegsRegisterClass()

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