| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.td | 54 def R18 : AVRReg<18, "r18">, DwarfRegNum<[18]>;
86 def R19R18 : AVRReg<18, "r19:r18", [R18, R19]>, DwarfRegNum<[18]>;
102 def R18R17 : AVRReg<17, "r18:r17", [R17, R18]>, DwarfRegNum<[17]>;
116 add R24, R25, R18, R19, R20, R21, R22, R23,
131 add R24, R25, R18, R19, R20, R21, R22, R23,
139 (add R23, R22, R21, R20, R19, R18, R17, R16)>;
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| H A D | AVRCallingConv.td | 41 def CSR_NormalTiny : CalleeSavedRegs<(add R29, R28, R19, R18)>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiCallingConv.td | 24 CCAssignToReg<[R6, R7, R18, R19]>>>>,
36 CCIfNotVarArg<CCIfType<[i32], CCAssignToReg<[ R6, R7, R18, R19 ]>>>,
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| H A D | LanaiRegisterInfo.td | 48 R6, R7, R18, R19, // registers for passing arguments
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiBaseInfo.h | 85 case Lanai::R18: in getLanaiRegisterNumbering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 116 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
125 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
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| H A D | HexagonFrameLowering.h | 97 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 }, in getCalleeSavedSpillSlots()
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| H A D | HexagonRegisterInfo.td | 146 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>;
539 (add R23, R22, R21, R20, R19, R18, R17, R16,
643 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23,
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| /freebsd/sys/contrib/edk2/Include/Protocol/ |
| H A D | DebugSupport.h | 305 UINT64 R18; member
774 UINT64 R18; member
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| /freebsd/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-am642-evm-nand.dtso | 43 AM64X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (R18) GPMC0_OEn_REn */
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| H A D | k3-am62-verdin-zinnia.dtsi | 135 AM62X_IOPAD(0x0098, PIN_INPUT, 7) /* (R18) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */
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| H A D | k3-am62-verdin-ivy.dtsi | 238 <AM62X_IOPAD(0x0098, PIN_INPUT, 7)>, /* (R18) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 164 Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 306 ENTRY(R18) \
340 ENTRY(R18) \
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 300 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
322 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYRegisterInfo.td | 70 def R18 : CSKYReg<18, "r18", ["t2"]>, DwarfRegNum<[18]>;
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| H A D | CSKYFrameLowering.cpp | 388 static const MCPhysReg CSHRegs[] = {CSKY::R18, CSKY::R19, CSKY::R20, in determineCalleeSaves()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 127 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchRegisterInfo.td | 78 def R18 : LoongArchReg<18, "r18", ["t6"]>, DwarfRegNum<[18]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 646 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in DecodeIntRegsRegisterClass()
661 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in DecodeGeneralSubRegsRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/ |
| H A D | AVRDisassembler.cpp | 65 AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/ |
| H A D | CSKYDisassembler.cpp | 68 CSKY::R14, CSKY::R15, CSKY::R16, CSKY::R17, CSKY::R18, CSKY::R19, CSKY::R20,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 757 Register = Hexagon::R18; in compoundRegisterMap()
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| H A D | HexagonMCDuplexInfo.cpp | 678 case Hexagon::R18: in addOps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.td | 306 def R18 : X86Reg<"r18", 18, [R18D]>, DwarfRegNum<[132, -2, -2]>;
593 R18, R19, R22, R23, R24, R25, R26, R27, R30, R31, RBX,
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