| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.td | 53 def R17 : AVRReg<17, "r17">, DwarfRegNum<[17]>;
87 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>;
102 def R18R17 : AVRReg<17, "r18:r17", [R17, R18]>, DwarfRegNum<[17]>;
120 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
135 R28, R29, R17, R16)>;
139 (add R23, R22, R21, R20, R19, R18, R17, R16)>;
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| H A D | AVRSubtarget.h | 95 return hasTinyEncoding() ? AVR::R17 : AVR::R1; in getELFArch()
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| H A D | AVRRegisterInfo.cpp | 71 for (unsigned Reg = AVR::R2; Reg <= AVR::R17; Reg++) in getReservedRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiBaseInfo.h | 83 case Lanai::R17: in getLanaiRegisterNumbering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiRegisterInfo.td | 46 (add R3, R9, R12, R13, R14, R16, R17,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 116 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
125 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
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| H A D | HexagonFrameLowering.h | 96 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, in getCalleeSavedSpillSlots()
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| H A D | HexagonRegisterInfo.td | 145 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>;
539 (add R23, R22, R21, R20, R19, R18, R17, R16,
643 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23,
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| H A D | HexagonFrameLowering.cpp | 1070 Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18, in insertCFIInstructionsAt()
1231 case Hexagon::R17: in getSpillFunctionFor()
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| /freebsd/sys/contrib/edk2/Include/Protocol/ |
| H A D | DebugSupport.h | 304 UINT64 R17; member
773 UINT64 R17; member
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| /freebsd/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-am642-evm-nand.dtso | 41 AM64X_IOPAD(0x007c, PIN_OUTPUT, 0) /* (R17) GPMC0_CLK */
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| H A D | k3-am642-tqma64xxl-mbax4xxl.dts | 856 /* (R17) GPMC0_CLK.UART4_RTSn */
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 163 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 305 ENTRY(R17) \
339 ENTRY(R17) \
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 300 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
322 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYRegisterInfo.td | 69 def R17 : CSKYReg<17, "r17", ["l9"]>, DwarfRegNum<[17]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 127 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchRegisterInfo.td | 77 def R17 : LoongArchReg<17, "r17", ["t5"]>, DwarfRegNum<[17]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 646 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in DecodeIntRegsRegisterClass()
661 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in DecodeGeneralSubRegsRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/ |
| H A D | AVRDisassembler.cpp | 65 AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/ |
| H A D | CSKYDisassembler.cpp | 68 CSKY::R14, CSKY::R15, CSKY::R16, CSKY::R17, CSKY::R18, CSKY::R19, CSKY::R20,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 760 Register = Hexagon::R17; in compoundRegisterMap()
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| H A D | HexagonMCDuplexInfo.cpp | 677 case Hexagon::R17: in addOps()
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| H A D | HexagonMCInstrInfo.cpp | 293 case R17: in getDuplexRegisterNumbering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.td | 305 def R17 : X86Reg<"r17", 17, [R17D]>, DwarfRegNum<[131, -2, -2]>;
592 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, R16, R17,
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