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/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78460.dtsi82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
86 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
87 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
88 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
89 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
90 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
91 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
[all …]
H A Darmada-xp-mv78260.dtsi65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
71 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
72 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
73 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
[all …]
H A Darmada-xp-mv78230.dtsi64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
69 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
71 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
72 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
73 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
[all …]
H A Darmada-385.dtsi52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
54 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
55 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
56 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
57 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
58 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
59 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
H A Darmada-380.dtsi53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
55 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
56 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
57 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
58 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
H A Darmada-xp-db.dts192 /* Port 0, Lane 0 */
196 /* Port 0, Lane 1 */
200 /* Port 0, Lane 2 */
204 /* Port 0, Lane 3 */
208 /* Port 2, Lane 0 */
212 /* Port 3, Lane 0 */
/linux/drivers/usb/serial/
H A Dio_ionsp.h124 #define IOSP_BUILD_DATA_HDR1(Port, Len) ((__u8) (((Port) | ((__u8) (((__u16) (Len)) >> 5) & 0x78))… argument
125 #define IOSP_BUILD_DATA_HDR2(Port, Len) ((__u8) (Len)) argument
131 #define IOSP_BUILD_CMD_HDR1(Port, Cmd) ((__u8) (IOSP_CMD_STAT_BIT | (Port) | ((__u8) ((Cmd) << 3))… argument
193 #define MAKE_CMD_WRITE_REG(ppBuf, pLen, Port, Reg, Val) \ argument
195 (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), \
203 #define MAKE_CMD_EXT_CMD(ppBuf, pLen, Port, ExtCmd, Param) \ argument
205 (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), IOSP_EXT_CMD); \
/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
[all …]
/linux/drivers/usb/typec/tcpm/
H A DKconfig4 tristate "USB Type-C Port Controller Manager"
9 The Type-C Port Controller Manager provides a USB PD and USB Type-C
10 state machine for use with Type-C Port Controllers.
15 tristate "Type-C Port Controller Interface driver"
19 Type-C Port Controller driver for TCPCI-compliant controller.
27 Type-C Port Controller Manager to provide USB PD and USB
35 USB Type-C. It works with Type-C Port Controller Manager
43 USB Type-C. It works with Type-C Port Controller Manager
53 with Type-C Port Controller Manager.
63 Type-C Port Controller Manager to provide USB PD and USB
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8750-qrd.dts980 * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
981 * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
982 * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST)
983 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
984 * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
985 * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
1003 * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
1004 * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
1005 * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST)
1006 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
[all …]
H A Dsm8650-qrd.dts1083 * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
1084 * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
1085 * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST)
1086 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
1087 * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
1088 * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
1106 * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
1107 * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
1108 * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST)
1109 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
[all …]
H A Dsm8650-hdk.dts1131 * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
1132 * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
1133 * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST)
1134 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
1135 * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
1136 * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
1154 * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
1155 * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
1156 * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST)
1157 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
[all …]
H A Dsm8750-mtp.dts1093 * WSA8835 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
1094 * WSA8835 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
1095 * WSA8835 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST)
1096 * WSA8835 Port 4 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
1113 * WSA8835 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
1114 * WSA8835 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
1115 * WSA8835 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST)
1116 * WSA8835 Port 4 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI)
1131 * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R)
1132 * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH)
[all …]
H A Dqcm6490-idp.dts852 * WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R)
853 * WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH)
854 * WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R)
855 * WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO)
856 * WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD)
877 * WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2
878 * WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2
879 * WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3
880 * WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4
/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_3xxx.dts208 reg = <0x3>; /* Port */
215 reg = <0x4>; /* Port */
220 reg = <0x5>; /* Port */
225 reg = <0x6>; /* Port */
230 reg = <0x7>; /* Port */
235 reg = <0x8>; /* Port */
240 reg = <0x9>; /* Port */
245 reg = <0xa>; /* Port */
250 reg = <0xb>; /* Port */
255 reg = <0xc>; /* Port */
[all …]
H A Docteon_68xx.dts269 reg = <0x0>; /* Port */
275 reg = <0x1>; /* Port */
281 reg = <0x2>; /* Port */
287 reg = <0x3>; /* Port */
301 reg = <0x0>; /* Port */
307 reg = <0x1>; /* Port */
313 reg = <0x2>; /* Port */
319 reg = <0x3>; /* Port */
333 reg = <0x0>; /* Port */
339 reg = <0x1>; /* Port */
[all …]
/linux/Documentation/driver-api/tty/
H A Dtty_port.rst4 TTY Port
15 The reference and details are contained in the `TTY Port Reference`_ and `TTY
16 Port Operations Reference`_ sections at the bottom.
18 TTY Port Functions
59 TTY Port Reference
67 TTY Port Operations Reference
/linux/Documentation/arch/s390/
H A Dqeth.rst5 OSA and HiperSockets Bridge Port Support
12 a primary or a secondary Bridge Port. For more information, see
15 When run on an OSA or HiperSockets Bridge Capable Port hardware, and the state
16 of some configured Bridge Port device on the channel changes, a udev
21 indicates that the Bridge Port device changed
30 When run on HiperSockets Bridge Capable Port hardware with host address
39 deregistered on the Bridge Port HiperSockets channel, or address
/linux/Documentation/driver-api/cxl/platform/
H A Dcdat.rst93 Port X ID : 0100 <- First port, 0100h represents an upstream port
94 Port Y ID : 0000 <- Second port, downstream port 0
95 Latency : 0100 <- Port latency
98 Port X ID : 0100
99 Port Y ID : 0001
112 Port X ID : 0100 <- First port, 0100h represents an upstream port
113 Port Y ID : FFFF <- Second port, FFFFh indicates any port
114 Bandwidth : 1200 <- Port bandwidth
/linux/Documentation/driver-api/cxl/platform/acpi/
H A Dsrat.rst47 Generic Port Affinity
49 The Generic Port Affinity subtable provides an association between a proximity
50 domain and a device handle representing a Generic Port such as a CXL host
52 from the SRAT for the path between CPU(s) (initiator) and the Generic Port.
58 Subtable Type : 06 [Generic Port Affinity]
70 The driver uses the association to retrieve the Generic Port performance
/linux/Documentation/gpu/dp-mst/
H A Dtopology-figure-2.dot47 port1 [label="Port #1"];
48 port2 [label="Port #2"];
49 port3 [label="Port #3"];
50 port4 [label="Port #4";style=filled;fillcolor=grey];
H A Dtopology-figure-3.dot50 port1 [label="Port #1"];
51 port2 [label="Port #2";penwidth=5];
52 port3 [label="Port #3";penwidth=3];
53 port4 [label="Port #4";style=filled;fillcolor=grey];
H A Dtopology-figure-1.dot48 port1 [label="Port #1";shape=oval];
49 port2 [label="Port #2";shape=oval];
50 port3 [label="Port #3";shape=oval];
51 port4 [label="Port #4";shape=oval];
/linux/Documentation/devicetree/bindings/net/
H A Dcavium-pip.txt62 reg = <0x0>; /* Port */
68 reg = <0x1>; /* Port */
74 reg = <0x2>; /* Port */
80 reg = <0x3>; /* Port */
94 reg = <0x0>; /* Port */
/linux/arch/arc/boot/dts/
H A Dabilis_tb100.dtsi30 /* Port 1 */
43 /* Port 2 */
56 /* Port 3 */
69 /* Port 4 */
82 /* Port 5 */
95 /* Port 6 */
111 /* Port 7 */
124 /* Port 8 */
128 /* Port 9 */

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