Searched refs:PixelClockBackEnd (Results 1 – 5 of 5) sorted by relevance
546 double PixelClockBackEnd[DML2_MAX_PLANES]; member866 double PixelClockBackEnd[DML2_MAX_PLANES]; member1122 double PixelClockBackEnd[DML2_MAX_PLANES]; member1233 double PixelClockBackEnd[DML2_MAX_PLANES]; member
145 …_for_progressive_to_interlace_unit(display_cfg, mode_lib->ip.ptoi_supported, s->PixelClockBackEnd); in dcn5_mode_programming()302 s->PixelClockBackEnd[k], in dcn5_mode_programming()
5326 …ce_unit(const struct dml2_display_cfg *display_cfg, bool ptoi_supported, double *PixelClockBackEnd) in dcn5_adjust_pixel_clock_for_progressive_to_interlace_unit() argument5332 …PixelClockBackEnd[k] = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].… in dcn5_adjust_pixel_clock_for_progressive_to_interlace_unit()
626 dml_float_t PixelClockBackEnd[__DML_NUM_PLANES__]; member
896 out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00; in populate_dml_output_cfg_from_stream_state()