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Searched refs:PixelClockBackEnd (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.h259 double PixelClockBackEnd,
330 double PixelClockBackEnd,
H A Ddisplay_mode_vba_util_32.c1346 double PixelClockBackEnd, in dml32_CalculateOutputLink() argument
1379 PixelClockBackEnd, ForcedOutputLinkBPP, false, Output, OutputFormat, in dml32_CalculateOutputLink()
1406 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1415 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1428 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1438 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1451 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1459 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1474 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1485 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
[all …]
H A Ddisplay_mode_vba_32.c348 v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 12 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
352 v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 6 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
356 v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 3 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
370 mode_lib->vba.PixelClockBackEnd[k], mode_lib->vba.ip.dsc_delay_factor_wa); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2097 mode_lib->vba.PixelClockBackEnd[k], in dml32_ModeSupportAndSystemConfigurationFull()
2418 mode_lib->vba.PixelClockBackEnd[k], in dml32_ModeSupportAndSystemConfigurationFull()
2466 …if (mode_lib->vba.PixelClockBackEnd[k] / 12.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->v… in dml32_ModeSupportAndSystemConfigurationFull()
2470 …if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vb… in dml32_ModeSupportAndSystemConfigurationFull()
2473 …if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vb… in dml32_ModeSupportAndSystemConfigurationFull()
2528 mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k], in dml32_ModeSupportAndSystemConfigurationFull()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_mode_vba_20.c1787 mode_lib->vba.PixelClockBackEnd[k] / 6 in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1794 mode_lib->vba.PixelClockBackEnd[k] / 3 in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1839 / mode_lib->vba.PixelClockBackEnd[k]; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4060 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20_ModeSupportAndSystemConfigurationFull()
4076 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4083 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4105 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4112 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4136 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4143 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
H A Ddisplay_mode_vba_20v2.c1823 mode_lib->vba.PixelClockBackEnd[k] / 6 in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1830 mode_lib->vba.PixelClockBackEnd[k] / 3 in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1875 / mode_lib->vba.PixelClockBackEnd[k]; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4174 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20v2_ModeSupportAndSystemConfigurationFull()
4191 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4199 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4222 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4230 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4255 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4263 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_mode_vba_21.c1779 mode_lib->vba.PixelClockBackEnd[k] / 6 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1786 mode_lib->vba.PixelClockBackEnd[k] / 3 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1831 / mode_lib->vba.PixelClockBackEnd[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4268 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml21_ModeSupportAndSystemConfigurationFull()
4285 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4293 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4316 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4324 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4349 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4357 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_mode_vba_314.c2259 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
2262 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
2265 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
2303 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
4359 if (v->PixelClockBackEnd[k] > 3200) {
4360 v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
4361 } else if (v->PixelClockBackEnd[k] > 1360) {
4363 } else if (v->PixelClockBackEnd[k] > 680) {
4365 } else if (v->PixelClockBackEnd[k] > 340) {
4388 v->PixelClockBackEnd[k],
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c2250 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
2253 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
2256 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
2293 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
4281 if (v->PixelClockBackEnd[k] > 3200) {
4282 v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
4283 } else if (v->PixelClockBackEnd[k] > 1360) {
4285 } else if (v->PixelClockBackEnd[k] > 680) {
4287 } else if (v->PixelClockBackEnd[k] > 340) {
4310 v->PixelClockBackEnd[k],
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_shared.c44 static void PixelClockAdjustmentForProgressiveToInterlaceUnit(const struct dml2_display_cfg *display_cfg, bool ptoi_supported, double *PixelClockBackEnd);
397 double PixelClockBackEnd,
448 double PixelClockBackEnd);
828 PixelClockAdjustmentForProgressiveToInterlaceUnit(display_cfg, mode_lib->ip.ptoi_supported, s->PixelClockBackEnd); in dml2_core_shared_mode_support()
1223 if (s->PixelClockBackEnd[k] > 4800) { in dml2_core_shared_mode_support()
1224 mode_lib->ms.support.NumberOfDSCSlices[k] = (unsigned int)(math_ceil2(s->PixelClockBackEnd[k] / 600, 4)); in dml2_core_shared_mode_support()
1225 } else if (s->PixelClockBackEnd[k] > 2400) { in dml2_core_shared_mode_support()
1227 } else if (s->PixelClockBackEnd[k] > 1200) { in dml2_core_shared_mode_support()
1229 } else if (s->PixelClockBackEnd[k] > 340) { in dml2_core_shared_mode_support()
1256 s->PixelClockBackEnd[ in dml2_core_shared_mode_support()
3082 PixelClockAdjustmentForProgressiveToInterlaceUnit(const struct dml2_display_cfg * display_cfg,bool ptoi_supported,double * PixelClockBackEnd) PixelClockAdjustmentForProgressiveToInterlaceUnit() argument
6663 CalculateOutputLink(struct dml2_core_internal_scratch * s,double PHYCLK,double PHYCLKD18,double PHYCLKD32,double Downspreading,bool IsMainSurfaceUsingTheIndicatedTiming,enum dml2_output_encoder_class Output,enum dml2_output_format_class OutputFormat,unsigned int HTotal,unsigned int HActive,double PixelClockBackEnd,double ForcedOutputLinkBPP,unsigned int DSCInputBitPerComponent,unsigned int NumberOfDSCSlices,double AudioSampleRate,unsigned int AudioSampleLayout,enum dml2_odm_mode ODMModeNoDSC,enum dml2_odm_mode ODMModeDSC,enum dml2_dsc_enable_option DSCEnable,unsigned int OutputLinkDPLanes,enum dml2_output_link_dp_rate OutputLinkDPRate,bool * RequiresDSC,bool * RequiresFEC,double * OutBpp,enum dml2_core_internal_output_type * OutputType,enum dml2_core_internal_output_type_rate * OutputRate,unsigned int * RequiredSlots) CalculateOutputLink() argument
6949 DSCDelayRequirement(bool DSCEnabled,enum dml2_odm_mode ODMMode,unsigned int DSCInputBitPerComponent,double OutputBpp,unsigned int HActive,unsigned int HTotal,unsigned int NumberOfDSCSlices,enum dml2_output_format_class OutputFormat,enum dml2_output_encoder_class Output,double PixelClock,double PixelClockBackEnd) DSCDelayRequirement() argument
[all...]
H A Ddml2_core_dcn4_calcs.c428 static void PixelClockAdjustmentForProgressiveToInterlaceUnit(const struct dml2_display_cfg *display_cfg, bool ptoi_supported, double *PixelClockBackEnd) in dml_is_420()
434 PixelClockBackEnd[k] = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000); in dml_is_420()
4168 double PixelClockBackEnd, in CalculateOutputLink()
4200 dml2_printf("DML::%s: PixelClockBackEnd = %f\n", __func__, PixelClockBackEnd); in CalculateOutputLink()
4214 *OutBpp = TruncToValidBPP(&s->TruncToValidBPP_locals, math_min2(600, PHYCLK) * 10, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, false, Output, in CalculateOutputLink()
4239 *OutBpp = TruncToValidBPP(&s->TruncToValidBPP_locals, (1 - Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, in CalculateOutputLink()
4244 *OutBpp = TruncToValidBPP(&s->TruncToValidBPP_locals, (1 - Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, in CalculateOutputLink()
4252 *OutBpp = TruncToValidBPP(&s->TruncToValidBPP_locals, (1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, in CalculateOutputLink()
4258 *OutBpp = TruncToValidBPP(&s->TruncToValidBPP_locals, (1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBP in CalculateOutputLink()
394 PixelClockAdjustmentForProgressiveToInterlaceUnit(const struct dml2_display_cfg * display_cfg,bool ptoi_supported,double * PixelClockBackEnd) PixelClockAdjustmentForProgressiveToInterlaceUnit() argument
4135 CalculateOutputLink(struct dml2_core_internal_scratch * s,double PHYCLK,double PHYCLKD18,double PHYCLKD32,double Downspreading,enum dml2_output_encoder_class Output,enum dml2_output_format_class OutputFormat,unsigned int HTotal,unsigned int HActive,double PixelClockBackEnd,double ForcedOutputLinkBPP,unsigned int DSCInputBitPerComponent,unsigned int NumberOfDSCSlices,double AudioSampleRate,unsigned int AudioSampleLayout,enum dml2_odm_mode ODMModeNoDSC,enum dml2_odm_mode ODMModeDSC,enum dml2_dsc_enable_option DSCEnable,unsigned int OutputLinkDPLanes,enum dml2_output_link_dp_rate OutputLinkDPRate,bool * RequiresDSC,bool * RequiresFEC,double * OutBpp,enum dml2_core_internal_output_type * OutputType,enum dml2_core_internal_output_type_rate * OutputRate,unsigned int * RequiredSlots) CalculateOutputLink() argument
4420 DSCDelayRequirement(bool DSCEnabled,enum dml2_odm_mode ODMMode,unsigned int DSCInputBitPerComponent,double OutputBpp,unsigned int HActive,unsigned int HTotal,unsigned int NumberOfDSCSlices,enum dml2_output_format_class OutputFormat,enum dml2_output_encoder_class Output,double PixelClock,double PixelClockBackEnd) DSCDelayRequirement() argument
[all...]
H A Ddml2_core_shared_types.h871 double PixelClockBackEnd[DML2_MAX_PLANES];
967 double PixelClockBackEnd[DML2_MAX_PLANES];
858 double PixelClockBackEnd[DML2_MAX_PLANES]; global() member
956 double PixelClockBackEnd[DML2_MAX_PLANES]; global() member
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_core.c83 dml_float_t PixelClockBackEnd,
744 dml_float_t PixelClockBackEnd);
2697 display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
5349 dml_float_t PixelClockBackEnd, in CalculateOutputLink() argument
5382 …ncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
5408 …- Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
5413 …- Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
5421 …- Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
5427 …- Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
5435 …- Downspreading / 100) * 20000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutpu… in CalculateOutputLink()
[all …]
H A Ddml2_utils.c124 dml_output_array->PixelClockBackEnd[dst_index] = dml_output_array->PixelClockBackEnd[src_index]; in dml2_util_copy_dml_output()
H A Ddisplay_mode_core_structs.h570 dml_float_t PixelClockBackEnd[__DML_NUM_PLANES__]; member
H A Ddml2_translation_helper.c840 out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00; in populate_dml_output_cfg_from_stream_state()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c2120 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2123 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2126 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2161 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4037 if (v->PixelClockBackEnd[k] > 3200) { in dml30_ModeSupportAndSystemConfigurationFull()
4038 v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); in dml30_ModeSupportAndSystemConfigurationFull()
4039 } else if (v->PixelClockBackEnd[k] > 1360) { in dml30_ModeSupportAndSystemConfigurationFull()
4041 } else if (v->PixelClockBackEnd[k] > 680) { in dml30_ModeSupportAndSystemConfigurationFull()
4043 } else if (v->PixelClockBackEnd[k] > 340) { in dml30_ModeSupportAndSystemConfigurationFull()
4066 v->PixelClockBackEnd[k], in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c706 mode_lib->vba.PixelClockBackEnd[mode_lib->vba.NumberOfActivePlanes] = dst->pixel_rate_mhz; in fetch_pipe_params()
1054 mode_lib->vba.PixelClockBackEnd[k] = mode_lib->vba.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
H A Ddisplay_mode_vba.h477 double PixelClockBackEnd[DC__NUM_DPP__MAX]; member