Searched refs:PRI (Results 1 – 10 of 10) sorted by relevance
124 return M(IN) | M(OUT) | M(PRI) | M(ERR) | M(NVAL) | in mangle_poll()133 return M(IN) | M(OUT) | M(PRI) | M(ERR) | M(NVAL) | in demangle_poll()
38 - BRI (S0) and PRI (S2M) interface
18 (PRI) allow devices to function much the same way as the CPU handling23 required to support the PCIe features ATS and PRI. ATS allows devices27 use the PRI in order to request the virtual address to be paged into the83 present, the device would request the page to be paged in via the PCIe PRI264 Interface (PRI). Once the OS has successfully completed the mapping, it
151 * Support device page faults (PCI PRI or SMMU Stall)
75 PRI, enumerator462 &ctx->pages[i + idx][PRI]) != 0) { in dax_lock_pages()
178 bool "PCI PRI support"181 PRI is the PCI Page Request Interface. It allows PCI devices that are
101 and PRI.
67 faults using the IOMMU HW's PRI (Page Request Interface). This queue object384 - PRI support with faults resolved in userspace
11 rate interfaces (PRI).
1421 mpam_write_partsel_reg(msc, PRI, pri_val); in mpam_reprogram_ris_partid()