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Searched refs:PP_CONTROL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_lvds.c221 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
265 lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL); in psb_intel_lvds_save()
316 REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL); in psb_intel_lvds_restore()
320 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_restore()
326 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_restore()
H A Dcdv_intel_dp.c389 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
392 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_on()
393 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
403 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
406 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_off()
407 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
422 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
426 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_on()
427 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
447 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
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H A Doaktrail_lvds.c47 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power()
58 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
H A Dcdv_intel_lvds.c118 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power()
129 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
H A Doaktrail_device.c175 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); in oaktrail_save_display_registers()
204 PSB_WVDC32(0, PP_CONTROL); in oaktrail_save_display_registers()
312 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); in oaktrail_restore_display_registers()
H A Dpsb_intel_reg.h168 #define PP_CONTROL 0x61204 macro
/linux/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c163 PP_CONTROL(display, 0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
216 val = intel_de_read(display, PP_CONTROL(display, 0)); in intel_lvds_pps_init_hw()
221 intel_de_write(display, PP_CONTROL(display, 0), val); in intel_lvds_pps_init_hw()
329 intel_de_rmw(display, PP_CONTROL(display, 0), 0, PANEL_POWER_ON); in intel_enable_lvds()
347 intel_de_rmw(display, PP_CONTROL(display, 0), PANEL_POWER_ON, 0); in intel_disable_lvds()
H A Dintel_dsi_vbt.c364 intel_de_rmw(display, PP_CONTROL(display, index), PANEL_POWER_ON, in icl_native_gpio_set_value()
371 intel_de_rmw(display, PP_CONTROL(display, index), EDP_BLC_ENABLE, in icl_native_gpio_set_value()