Searched refs:PP_CONTROL (Results 1 – 11 of 11) sorted by relevance
/linux/drivers/gpu/drm/gma500/ |
H A D | psb_intel_lvds.c | 220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power() 231 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power() 264 lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL); in psb_intel_lvds_save() 315 REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL); in psb_intel_lvds_restore() 319 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_restore() 325 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_restore()
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H A D | cdv_intel_dp.c | 388 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on() 391 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_on() 392 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on() 402 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off() 405 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_off() 406 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off() 421 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on() 425 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_on() 426 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on() 446 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off() [all …]
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H A D | oaktrail_lvds.c | 46 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power() 57 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
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H A D | cdv_intel_lvds.c | 117 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power() 128 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
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H A D | oaktrail_device.c | 175 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); in oaktrail_save_display_registers() 204 PSB_WVDC32(0, PP_CONTROL); in oaktrail_save_display_registers() 312 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); in oaktrail_restore_display_registers()
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H A D | cdv_device.c | 253 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); in cdv_save_display_registers() 336 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); in cdv_restore_display_registers()
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H A D | psb_intel_reg.h | 168 #define PP_CONTROL 0x61204 macro
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/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_lvds.c | 162 PP_CONTROL(dev_priv, 0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state() 215 val = intel_de_read(dev_priv, PP_CONTROL(dev_priv, 0)); in intel_lvds_pps_init_hw() 220 intel_de_write(dev_priv, PP_CONTROL(dev_priv, 0), val); in intel_lvds_pps_init_hw() 328 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), 0, PANEL_POWER_ON); in intel_enable_lvds() 346 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), PANEL_POWER_ON, 0); in intel_disable_lvds()
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H A D | intel_pps_regs.h | 48 #define PP_CONTROL(dev_priv, pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_CONTROL) macro
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H A D | intel_pps.c | 287 return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD; in pps_has_vdd_on() 517 regs->pp_ctrl = PP_CONTROL(display, pps_idx); in intel_pps_get_registers() 1795 intel_de_rmw(display, PP_CONTROL(display, pps_idx), in intel_pps_unlock_regs_wa() 1858 pp_reg = PP_CONTROL(display, 0); in assert_pps_unlocked() 1881 pp_reg = PP_CONTROL(display, pipe); in assert_pps_unlocked() 1886 pp_reg = PP_CONTROL(display, 0); in assert_pps_unlocked()
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H A D | intel_dsi_vbt.c | 357 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, index), PANEL_POWER_ON, in icl_native_gpio_set_value() 364 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, index), EDP_BLC_ENABLE, in icl_native_gpio_set_value()
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