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Searched refs:PORT_BASE (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/scsi/hisi_sas/
H A Dhisi_sas_v1_hw.c112 #define PORT_BASE (0x800) macro
114 #define PHY_CFG (PORT_BASE + 0x0)
119 #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc)
126 #define PHY_CTRL (PORT_BASE + 0x14)
129 #define PHY_RATE_NEGO (PORT_BASE + 0x30)
130 #define PHY_PCN (PORT_BASE + 0x44)
131 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
132 #define SL_CONTROL (PORT_BASE + 0x94)
135 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
136 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
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/linux/tools/testing/selftests/net/
H A Dpsock_fanout.c487 typeflags, (uint16_t)PORT_BASE, in test_datapath()
488 (uint16_t)(PORT_BASE + port_off)); in test_datapath()
503 pair_udp_open(fds_udp[0], PORT_BASE); in test_datapath()
504 pair_udp_open(fds_udp[1], PORT_BASE + port_off); in test_datapath()
H A Dpsock_lib.h23 #define PORT_BASE 8000 macro
H A Dpsock_tpacket.c229 pair_udp_open(udp_sock, PORT_BASE); in walk_v1_v2_rx()
590 pair_udp_open(udp_sock, PORT_BASE); in walk_v3_rx()
/linux/drivers/ata/
H A Dahci_ceva.c70 #define PORT_BASE 0x100 macro
183 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); in ahci_ceva_setup()
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_regs.h58 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) macro
59 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))