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Searched refs:PMSELR_EL0 (Results 1 – 5 of 5) sorted by relevance

/linux/arch/arm64/kvm/
H A Dsys_regs.c1163 __vcpu_assign_sys_reg(vcpu, PMSELR_EL0, p->regval); in access_pmselr()
1166 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) in access_pmselr()
1251 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, in access_pmu_evcntr()
1252 __vcpu_sys_reg(vcpu, PMSELR_EL0)); in access_pmu_evcntr()
1302 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); in access_pmu_evtyper()
3645 { PMU_SYS_REG(PMSELR_EL0),
3646 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
H A Demulate-nested.c578 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, in check_mdcr_hpmn()
579 __vcpu_sys_reg(vcpu, PMSELR_EL0)); in check_mdcr_hpmn()
1858 SR_FGT(SYS_PMSELR_EL0, HDFGRTR, PMSELR_EL0, 1),
/linux/Documentation/arch/arm64/
H A Dperf.rst129 In particular, the PMSELR_EL0 register is zeroed each time the sequence lock is
/linux/arch/arm64/include/asm/
H A Dkvm_host.h474 PMSELR_EL0, /* Event Counter Selection Register */ enumerator
/linux/arch/arm64/tools/
H A Dsysreg3630 Sysreg PMSELR_EL0 3 3 9 12 5
4406 Field 19 PMSELR_EL0
4470 Field 19 PMSELR_EL0